diff --git a/flake.lock b/flake.lock index 44c4738..3754b8d 100644 --- a/flake.lock +++ b/flake.lock @@ -37,11 +37,11 @@ ] }, "locked": { - "lastModified": 1770895474, - "narHash": "sha256-JBcrq1Y0uw87VZdYsByVbv+GBuT6ECaCNb9txLX9UuU=", + "lastModified": 1771610171, + "narHash": "sha256-+DeInuhbm6a6PpHDNUS7pozDouq2+8xSDefoNaZLW0E=", "owner": "hyprwm", "repo": "aquamarine", - "rev": "a494d50d32b5567956b558437ceaa58a380712f7", + "rev": "7f9eb087703ec4acc6b288d02fa9ea3db803cd3d", "type": "github" }, "original": { @@ -155,6 +155,38 @@ "type": "github" } }, + "cachyos-kernel": { + "flake": false, + "locked": { + "lastModified": 1771517207, + "narHash": "sha256-+zDtnmXNyMd3hMepErdPDZzqYS0PiZA0Anbbx9Pvs4g=", + "owner": "CachyOS", + "repo": "linux-cachyos", + "rev": "39737576a25091a3c4ca00729b769a1f92ec98d5", + "type": "github" + }, + "original": { + "owner": "CachyOS", + "repo": "linux-cachyos", + "type": "github" + } + }, + "cachyos-kernel-patches": { + "flake": false, + "locked": { + "lastModified": 1771516433, + "narHash": "sha256-SuockPZgd2bfjWGmdT8AUBTnBZWvxdA+b8Ss98lNC6c=", + "owner": "CachyOS", + "repo": "kernel-patches", + "rev": "505aef2086e584ba683a5ac1cb8ed8252fea2cfd", + "type": "github" + }, + "original": { + "owner": "CachyOS", + "repo": "kernel-patches", + "type": "github" + } + }, "curl-src": { "flake": false, "locked": { @@ -205,6 +237,22 @@ } }, "flake-compat_2": { + "flake": false, + "locked": { + "lastModified": 1767039857, + "narHash": "sha256-vNpUSpF5Nuw8xvDLj2KCwwksIbjua2LZCqhV1LNRDns=", + "owner": "NixOS", + "repo": "flake-compat", + "rev": "5edf11c44bc78a0d334f6334cdaf7d60d732daab", + "type": "github" + }, + "original": { + "owner": "NixOS", + "repo": "flake-compat", + "type": "github" + } + }, + "flake-compat_3": { "locked": { "lastModified": 1761640442, "narHash": "sha256-AtrEP6Jmdvrqiv4x2xa5mrtaIp3OEe8uBYCDZDS+hu8=", @@ -220,6 +268,24 @@ } }, "flake-parts": { + "inputs": { + "nixpkgs-lib": "nixpkgs-lib" + }, + "locked": { + "lastModified": 1769996383, + "narHash": "sha256-AnYjnFWgS49RlqX7LrC4uA+sCCDBj0Ry/WOJ5XWAsa0=", + "owner": "hercules-ci", + "repo": "flake-parts", + "rev": "57928607ea566b5db3ad13af0e57e921e6b12381", + "type": "github" + }, + "original": { + "owner": "hercules-ci", + "repo": "flake-parts", + "type": "github" + } + }, + "flake-parts_2": { "inputs": { "nixpkgs-lib": [ "nixvim", @@ -240,7 +306,7 @@ "type": "github" } }, - "flake-parts_2": { + "flake-parts_3": { "inputs": { "nixpkgs-lib": [ "stylix", @@ -360,11 +426,11 @@ ] }, "locked": { - "lastModified": 1770915843, - "narHash": "sha256-ZwU5wXKNqpOQvjNz6aBp1j5peiBZow1++6pLnk5VAhs=", + "lastModified": 1771851181, + "narHash": "sha256-gFgE6mGUftwseV3DUENMb0k0EiHd739lZexPo5O/sdQ=", "owner": "nix-community", "repo": "home-manager", - "rev": "6a1f7101d2c3ee87d485a87880d73b4665c6a4bd", + "rev": "9a4b494b1aa1b93d8edf167f46dc8e0c0011280c", "type": "github" }, "original": { @@ -448,11 +514,11 @@ "xdph": "xdph" }, "locked": { - "lastModified": 1771336666, - "narHash": "sha256-b3UT9mOjQTNwfT/MHO3ZpBHlAvTC+BaqUokqS0VEgRo=", + "lastModified": 1772022552, + "narHash": "sha256-L3zktLSXcvsqczTz7YL5PXYgn4a08tRfl9t6YYLESM8=", "owner": "hyprwm", "repo": "Hyprland", - "rev": "0de216e783d02748183ac5a5712201517685f492", + "rev": "457617b5a31f70ea63e1fcc0729f29e4a9e6b486", "type": "github" }, "original": { @@ -524,11 +590,11 @@ ] }, "locked": { - "lastModified": 1770899531, - "narHash": "sha256-UBrWjh0DR8db60aLNkTnZTJ9F4kWK0Y7rUDNJC88W7A=", + "lastModified": 1771865848, + "narHash": "sha256-xwNa+1D8WPsDnJtUofDrtyDCZKZotbUymzV/R5s+M0I=", "owner": "hyprwm", "repo": "hyprland-plugins", - "rev": "e03c34ccd51280a44ea6d1f5c040cd81ecca25ed", + "rev": "b85a56b9531013c79f2f3846fd6ee2ff014b8960", "type": "github" }, "original": { @@ -578,11 +644,11 @@ ] }, "locked": { - "lastModified": 1767983607, - "narHash": "sha256-8C2co8NYfR4oMOUEsPROOJ9JHrv9/ktbJJ6X1WsTbXc=", + "lastModified": 1771866172, + "narHash": "sha256-fYFoXhQLrm1rD8vSFKQBOEX4OGCuJdLt1amKfHd5GAw=", "owner": "hyprwm", "repo": "hyprlang", - "rev": "d4037379e6057246b408bbcf796cf3e9838af5b2", + "rev": "0b219224910e7642eb0ed49f0db5ec3d008e3e41", "type": "github" }, "original": { @@ -655,11 +721,11 @@ ] }, "locked": { - "lastModified": 1770139857, - "narHash": "sha256-bCqxcXjavgz5KBJ/1CBLqnagMMf9JvU1m9HmYVASKoc=", + "lastModified": 1771271487, + "narHash": "sha256-41gEiUS0Pyw3L/ge1l8MXn61cK14VAhgWB/JV8s/oNI=", "owner": "hyprwm", "repo": "hyprutils", - "rev": "9038eec033843c289b06b83557a381a2648d8fa5", + "rev": "340a792e3b3d482c4ae5f66d27a9096bdee6d76d", "type": "github" }, "original": { @@ -709,11 +775,11 @@ ] }, "locked": { - "lastModified": 1770203293, - "narHash": "sha256-PR/KER+yiHabFC/h1Wjb+9fR2Uy0lWM3Qld7jPVaWkk=", + "lastModified": 1771606233, + "narHash": "sha256-F3PLUqQ/TwgR70U+UeOqJnihJZ2EuunzojYC4g5xHr0=", "owner": "hyprwm", "repo": "hyprwire", - "rev": "37bc90eed02b0c8b5a77a0b00867baf3005cfb98", + "rev": "06c7f1f8c4194786c8400653c4efc49dc14c0f3a", "type": "github" }, "original": { @@ -809,11 +875,11 @@ }, "master": { "locked": { - "lastModified": 1770926019, - "narHash": "sha256-A6kvW7byN8SjNI8zrP+LtfOMqGZFrjEBm7TXLYDLzA0=", + "lastModified": 1772051972, + "narHash": "sha256-qUGo6noKFC17GJlPumIJcJnAIu5oouJA6fBtFuLgJz0=", "owner": "NixOS", "repo": "nixpkgs", - "rev": "f1d249ec713867f5eedaf4b14b89a9d73cdb2d58", + "rev": "4f63959d174c1e233df4b8a0a0d7482e670949eb", "type": "github" }, "original": { @@ -845,11 +911,11 @@ }, "locked": { "dir": "packages/nix", - "lastModified": 1770491303, - "narHash": "sha256-JMN7T1ZrQ7PjSsgKobxtEENHiBAxqHNNIAaJcPnCeHM=", + "lastModified": 1771985657, + "narHash": "sha256-wAnrrFZxuHrITZAfyUyuIItYW/2gjO+gm3TCupExdt4=", "owner": "SteamClientHomebrew", "repo": "Millennium", - "rev": "5089051787adb186aa7ff0bea54d3d7cd5e67539", + "rev": "dbbb365d32725022041caa2d2211f7934ca8ef58", "type": "github" }, "original": { @@ -948,17 +1014,40 @@ "type": "gitlab" } }, - "nixos-apple-silicon": { + "nix-cachyos-kernel": { "inputs": { + "cachyos-kernel": "cachyos-kernel", + "cachyos-kernel-patches": "cachyos-kernel-patches", "flake-compat": "flake-compat_2", + "flake-parts": "flake-parts", "nixpkgs": "nixpkgs_3" }, "locked": { - "lastModified": 1770630652, - "narHash": "sha256-/fhL3g+Rp16vvsNPijhLgBuZeYCv7VJr6OTJpA0ZRnw=", + "lastModified": 1771525883, + "narHash": "sha256-XqDuaRbxLGno5HcWRE5lQrgMBeXXs6ncGq+R6eCvsq8=", + "owner": "xddxdd", + "repo": "nix-cachyos-kernel", + "rev": "15fb6039dd248d478a8f3f7f6c067b206da2bf54", + "type": "github" + }, + "original": { + "owner": "xddxdd", + "ref": "release", + "repo": "nix-cachyos-kernel", + "type": "github" + } + }, + "nixos-apple-silicon": { + "inputs": { + "flake-compat": "flake-compat_3", + "nixpkgs": "nixpkgs_4" + }, + "locked": { + "lastModified": 1771511514, + "narHash": "sha256-qhtonMK07BCVC/wZ+pZ9/MKhcTric7YUaCpW6pOg8IM=", "owner": "tpwrules", "repo": "nixos-apple-silicon", - "rev": "f2936008b132717d7cc4616bbac56f7478bb0a58", + "rev": "2b92d495204be0b10845c66361444dbc8441c68d", "type": "github" }, "original": { @@ -969,11 +1058,11 @@ }, "nixpkgs": { "locked": { - "lastModified": 1770841267, - "narHash": "sha256-9xejG0KoqsoKEGp2kVbXRlEYtFFcDTHjidiuX8hGO44=", + "lastModified": 1771848320, + "narHash": "sha256-0MAd+0mun3K/Ns8JATeHT1sX28faLII5hVLq0L3BdZU=", "owner": "NixOS", "repo": "nixpkgs", - "rev": "ec7c70d12ce2fc37cb92aff673dcdca89d187bae", + "rev": "2fc6539b481e1d2569f25f8799236694180c0993", "type": "github" }, "original": { @@ -983,6 +1072,21 @@ "type": "github" } }, + "nixpkgs-lib": { + "locked": { + "lastModified": 1769909678, + "narHash": "sha256-cBEymOf4/o3FD5AZnzC3J9hLbiZ+QDT/KDuyHXVJOpM=", + "owner": "nix-community", + "repo": "nixpkgs.lib", + "rev": "72716169fe93074c333e8d0173151350670b824c", + "type": "github" + }, + "original": { + "owner": "nix-community", + "repo": "nixpkgs.lib", + "type": "github" + } + }, "nixpkgs_2": { "locked": { "lastModified": 1770115704, @@ -1000,6 +1104,22 @@ } }, "nixpkgs_3": { + "locked": { + "lastModified": 1771482645, + "narHash": "sha256-MpAKyXfJRDTgRU33Hja+G+3h9ywLAJJNRq4Pjbb4dQs=", + "owner": "NixOS", + "repo": "nixpkgs", + "rev": "724cf38d99ba81fbb4a347081db93e2e3a9bc2ae", + "type": "github" + }, + "original": { + "owner": "NixOS", + "ref": "nixos-unstable-small", + "repo": "nixpkgs", + "type": "github" + } + }, + "nixpkgs_4": { "locked": { "lastModified": 1768305791, "narHash": "sha256-AIdl6WAn9aymeaH/NvBj0H9qM+XuAuYbGMZaP0zcXAQ=", @@ -1015,13 +1135,13 @@ "type": "github" } }, - "nixpkgs_4": { + "nixpkgs_5": { "locked": { - "lastModified": 1770562336, - "narHash": "sha256-ub1gpAONMFsT/GU2hV6ZWJjur8rJ6kKxdm9IlCT0j84=", + "lastModified": 1771848320, + "narHash": "sha256-0MAd+0mun3K/Ns8JATeHT1sX28faLII5hVLq0L3BdZU=", "owner": "NixOS", "repo": "nixpkgs", - "rev": "d6c71932130818840fc8fe9509cf50be8c64634f", + "rev": "2fc6539b481e1d2569f25f8799236694180c0993", "type": "github" }, "original": { @@ -1030,7 +1150,7 @@ "type": "indirect" } }, - "nixpkgs_5": { + "nixpkgs_6": { "locked": { "lastModified": 1770380644, "narHash": "sha256-P7dWMHRUWG5m4G+06jDyThXO7kwSk46C1kgjEWcybkE=", @@ -1048,16 +1168,16 @@ }, "nixvim": { "inputs": { - "flake-parts": "flake-parts", - "nixpkgs": "nixpkgs_5", + "flake-parts": "flake-parts_2", + "nixpkgs": "nixpkgs_6", "systems": "systems_3" }, "locked": { - "lastModified": 1770630823, - "narHash": "sha256-5SEmOnJ61vmbap39vzWEsCX5UQ+3Ul8J4mXWKdqSn3w=", + "lastModified": 1771135771, + "narHash": "sha256-wyvBIhDuyCRyjB3yPg77qoyxrlgQtBR1rVW3c9knV3E=", "owner": "nix-community", "repo": "nixvim", - "rev": "6acc964664ac916c64fe4e394edd467af4d90790", + "rev": "ed0424f0b08d303a7348f52f7850ad1b2704f9ba", "type": "github" }, "original": { @@ -1070,14 +1190,15 @@ "inputs": { "nixpkgs": [ "nixpkgs" - ] + ], + "noctalia-qs": "noctalia-qs" }, "locked": { - "lastModified": 1770922006, - "narHash": "sha256-xg40mnp5KKBepACmvlPzmn5iPyUBxktfv50saSVUn0M=", + "lastModified": 1772037803, + "narHash": "sha256-307PELik0fSETKF0xwM2uAeIsFZTkOApEMnZ2wcTpA4=", "owner": "noctalia-dev", "repo": "noctalia-shell", - "rev": "d87364964948b9d691f8363f85a5e23bee154df9", + "rev": "2e43e5348e290220d65b024aa543fc672b05a3cc", "type": "github" }, "original": { @@ -1086,6 +1207,27 @@ "type": "github" } }, + "noctalia-qs": { + "inputs": { + "nixpkgs": [ + "noctalia", + "nixpkgs" + ] + }, + "locked": { + "lastModified": 1771796397, + "narHash": "sha256-lbZkAMNQl5Ymqhdvp46K8hubZ7n7KQRPnTP5bNJzMSk=", + "owner": "noctalia-dev", + "repo": "noctalia-qs", + "rev": "1711c5a20b74a31b703394164c5d2d9561f13ee9", + "type": "github" + }, + "original": { + "owner": "noctalia-dev", + "repo": "noctalia-qs", + "type": "github" + } + }, "nur": { "inputs": { "flake-parts": [ @@ -1121,11 +1263,11 @@ ] }, "locked": { - "lastModified": 1770726378, - "narHash": "sha256-kck+vIbGOaM/dHea7aTBxdFYpeUl/jHOy5W3eyRvVx8=", + "lastModified": 1771858127, + "narHash": "sha256-Gtre9YoYl3n25tJH2AoSdjuwcqij5CPxL3U3xysYD08=", "owner": "cachix", "repo": "git-hooks.nix", - "rev": "5eaaedde414f6eb1aea8b8525c466dc37bba95ae", + "rev": "49bbbfc218bf3856dfa631cead3b052d78248b83", "type": "github" }, "original": { @@ -1160,8 +1302,9 @@ "master": "master", "millennium": "millennium", "naviterm": "naviterm", + "nix-cachyos-kernel": "nix-cachyos-kernel", "nixos-apple-silicon": "nixos-apple-silicon", - "nixpkgs": "nixpkgs_4", + "nixpkgs": "nixpkgs_5", "nixvim": "nixvim", "noctalia": "noctalia", "stylix": "stylix", @@ -1175,7 +1318,7 @@ "base16-helix": "base16-helix", "base16-vim": "base16-vim", "firefox-gnome-theme": "firefox-gnome-theme", - "flake-parts": "flake-parts_2", + "flake-parts": "flake-parts_3", "gnome-shell": "gnome-shell", "nixpkgs": [ "nixpkgs" @@ -1189,11 +1332,11 @@ "tinted-zed": "tinted-zed" }, "locked": { - "lastModified": 1771330061, - "narHash": "sha256-qBWXy3mSOEYjvZB/RZHT0joVPhNWU8GQZQljLzyMTq0=", + "lastModified": 1771787992, + "narHash": "sha256-Vg4bGwwenNYI8p3nJTl9FRyeIyrjATeZrZr+GyUSDrw=", "owner": "nix-community", "repo": "stylix", - "rev": "fa45bf2d70517a8643a0edb44b02b8e6c0453d06", + "rev": "30054cca073b49b42a71289edec858f535b27fe9", "type": "github" }, "original": { @@ -1411,11 +1554,11 @@ ] }, "locked": { - "lastModified": 1770919290, - "narHash": "sha256-iJ9c0ZewfRRYUflaEOj43n5TWaB6Ezygn2UA/ZHGQJA=", + "lastModified": 1772005916, + "narHash": "sha256-aFYnT0gStcu1PVTh2Xzd0n8PIEKmqvTgrVkpv49qc6M=", "owner": "0xc000022070", "repo": "zen-browser-flake", - "rev": "0078cf2d5e81eb56a9356d51f2738f7141194de1", + "rev": "044299e83752f78f9fc5d6a648f7f3dd84bb3b18", "type": "github" }, "original": { diff --git a/flake.nix b/flake.nix index beea518..53cdbed 100644 --- a/flake.nix +++ b/flake.nix @@ -21,6 +21,7 @@ url = "gitlab:detoxify92/naviterm"; inputs.nixpkgs.follows = "nixpkgs"; }; + nix-cachyos-kernel.url = "github:xddxdd/nix-cachyos-kernel/release"; millennium.url = "github:SteamClientHomebrew/Millennium?dir=packages/nix"; master.url = "github:NixOS/nixpkgs/master"; home-manager.url = "github:nix-community/home-manager"; @@ -43,7 +44,7 @@ }; - outputs = { self, stylix, astal, nixpkgs, home-manager, zen-browser, master, nixos-apple-silicon, nixvim, noctalia,... }@inputs: + outputs = { self, stylix, astal, nixpkgs, home-manager, zen-browser, master, nixos-apple-silicon, nix-cachyos-kernel, nixvim, noctalia,... }@inputs: let system = "x86_64-linux"; lib = nixpkgs.lib; diff --git a/hosts/desktop/configuration.nix b/hosts/desktop/configuration.nix index 9800241..7d65200 100644 --- a/hosts/desktop/configuration.nix +++ b/hosts/desktop/configuration.nix @@ -1,6 +1,3 @@ -#Edit this configuration file to define what should be installed on -# your system. Help is available in the configuration.nix(5) man page -# and in the NixOS manual (accessible by running ‘nixos-help’). { config, pkgs, master, lib, pkgs-master, inputs, ... }: @@ -46,9 +43,13 @@ boot = { # Enable "Silent Boot" consoleLogLevel = 0; initrd.verbose = false; - kernelPackages = pkgs.linuxPackages_zen; + kernelPackages = pkgs.cachyosKernels.linuxPackages-cachyos-latest; kernelModules = [ "amdgpu" ]; kernelPatches = [ + /*{ + name = "frl"; + patch = ../../patches/0001-amdgpu-frl.patch; + }*/ /*{ name = "dsc"; patch = ../../patches/bigscreen_1.patch; @@ -152,11 +153,15 @@ boot = { services.greetd = { enable = true; settings = rec { - initial_session = { + hyprland_session = { command = "dbus-launch ${pkgs.hyprland}/bin/start-hyprland"; user = "joshuaelm"; }; - default_session = initial_session; + gamescope_session = { + command = "${lib.getExe pkgs.gamescope} -W 3840 -H 2160 -r 120 --hdr-enabled --adaptive-sync --rt --steam -- steam -gamepadui -steamdeck -steamos3 > /dev/null 2>&1"; + user = "joshuaelm"; + }; + default_session = hyprland_session; }; }; @@ -208,23 +213,6 @@ boot = { # use the example session manager (no others are packaged yet so this is enabled by default, # no need to redefine it in your config for now) #media-session.enable = true; - extraConfig.pipewire."92-low-latency" = { - "context.properties" = { - "default.clock.rate" = 48000; - "default.clock.quantum" = 32; - "default.clock.min-quantum" = 32; - "default.clock.max-quantum" = 32; - }; - }; - }; - services.pulseaudio.configFile = pkgs.runCommand "default.pa" {} '' - sed 's/module-udev-detect$/module-udev-detect tsched=0/' \ - ${pkgs.pulseaudio}/etc/pulse/default.pa > $out -''; - environment.etc."wireplumber/main.lua.d/90-suspend-timeout.lua" = { - text = '' - session.suspend-timeout-seconds = 0 - ''; }; services.pulseaudio.extraConfig = '' @@ -336,7 +324,7 @@ services.pulseaudio.extraConfig = '' ryubing gomatrix python3 - inputs.naviterm.packages.${pkgs.system}.default + #inputs.naviterm.packages.${pkgs.system}.default pavucontrol sbctl boxflat @@ -345,7 +333,7 @@ services.pulseaudio.extraConfig = '' corectrl wiremix steamtinkerlaunch - wineWowPackages.wayland + wineWow64Packages.wayland blueman lapce prismlauncher @@ -368,14 +356,19 @@ services.pulseaudio.extraConfig = '' services.xserver.enableTCP = true; services.sunshine = { - enable = true; + enable = false; autoStart = false; capSysAdmin = true; openFirewall = true; }; # Enable Steam - nixpkgs.overlays = [ inputs.millennium.overlays.default ]; + nixpkgs.overlays = [ + inputs.millennium.overlays.default + inputs.nix-cachyos-kernel.overlays.pinned + ]; + + programs.steam = { enable = true; remotePlay.openFirewall = true; # Open ports in the firewall for Steam Remote Play @@ -402,12 +395,12 @@ services.pulseaudio.extraConfig = '' nixpkgs.config.packageOverrides = pkgs: { steam = pkgs.steam.override { - extraLibraries = pkgs: [ pkgs.xorg.libxcb ]; + extraLibraries = pkgs: [ pkgs.libxcb ]; extraPkgs = pkgs: with pkgs; [ - xorg.libXcursor - xorg.libXi - xorg.libXinerama - xorg.libXScrnSaver + libXcursor + libXi + libXinerama + libXScrnSaver libpng libpulseaudio libvorbis @@ -420,7 +413,7 @@ services.pulseaudio.extraConfig = '' programs.gamescope = { enable = true; - capSysNice = false; + capSysNice = true; }; programs.nix-ld.enable = true; diff --git a/modules/hypr/default.nix b/modules/hypr/default.nix index 3d7cb4f..7abc8c9 100644 --- a/modules/hypr/default.nix +++ b/modules/hypr/default.nix @@ -18,7 +18,7 @@ # Monitors monitor = [ - "HDMI-A-1, 3840x2160@120, 0x0, auto, bitdepth, 10, sdrsaturation, 1, sdrbrightness, 1" + "HDMI-A-1, 3840x2160@120, 0x0, auto, bitdepth, 10" "eDP-1, 2560x1600@60, 0x0, 1.6" "DP-1, highres@highrr, 0x0, 1" ]; @@ -34,13 +34,6 @@ "" ]; - ecosystem = { - enforce_permissions = 1; - permission = [ - "/nix/store/[a-z0-9]{32}-hyprlock-[0-9.]*/bin/hyprlock, screencopy, allow" - "/nix/store/[a-z0-9]{32}-xdg-desktop-portal-hyprland-[0-9.]*/libexec/.xdg-desktop-portal-hyprland-wrapped, screencopy, allow" - ]; - }; # Debug settings debug.full_cm_proto = true; @@ -128,6 +121,7 @@ misc = { force_default_wallpaper = 0; enable_anr_dialog = 0; + vrr = 1; }; bind = [ diff --git a/modules/yazi/default.nix b/modules/yazi/default.nix index cbb0f82..44ed334 100644 --- a/modules/yazi/default.nix +++ b/modules/yazi/default.nix @@ -2,5 +2,6 @@ { programs.yazi = { enable = true; + shellWrapperName = "y"; }; } diff --git a/modules/zen/default.nix b/modules/zen/default.nix index c382b50..b480a1d 100644 --- a/modules/zen/default.nix +++ b/modules/zen/default.nix @@ -5,7 +5,7 @@ ]; programs.zen-browser = { enable = true; - + suppressXdgMigrationWarning = true; profiles = { default = { # bookmarks, extensions, search engines... diff --git a/patches/0001-amdgpu-frl.patch b/patches/0001-amdgpu-frl.patch new file mode 100644 index 0000000..0f80614 --- /dev/null +++ b/patches/0001-amdgpu-frl.patch @@ -0,0 +1,11685 @@ +diff --git a/.github/ISSUE_TEMPLATE/issue.md b/.github/ISSUE_TEMPLATE/issue.md +new file mode 100644 +index 000000000000..1cd10a4f2deb +--- /dev/null ++++ b/.github/ISSUE_TEMPLATE/issue.md +@@ -0,0 +1,10 @@ ++--- ++name: Issue ++about: Bug report ++title: '' ++labels: '' ++assignees: '' ++ ++--- ++ ++ +diff --git a/.github/workflows/genpatch.yml b/.github/workflows/genpatch.yml +new file mode 100644 +index 000000000000..a0dcad457f93 +--- /dev/null ++++ b/.github/workflows/genpatch.yml +@@ -0,0 +1,22 @@ ++name: Generate patch - Master branch ++on: ++ push: ++ branches: hdmi_frl ++ ++jobs: ++ generate_patch: ++ runs-on: ubuntu-24.04 ++ steps: ++ - name: Checkout repository ++ uses: actions/checkout@v4 ++ with: ++ ref: hdmi_frl ++ fetch-depth: 0 ++ - name: Generate patch ++ run: git diff origin/master > 0001-amdgpu-frl.patch ++ - name: Save artifacts ++ uses: actions/upload-artifact@v4 ++ with: ++ name: "Patch" ++ path: 0001-amdgpu-frl.patch ++ retention-days: 30 +diff --git a/.gitignore b/.gitignore +index 3a7241c941f5..d5dbc2628e85 100644 +--- a/.gitignore ++++ b/.gitignore +@@ -10,7 +10,7 @@ + # + # Normal rules (sorted alphabetically) + # +-.* ++. + *.a + *.asn1.[ch] + *.bin +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index 0b4fc654e76f..02d8e52c03bd 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -2062,6 +2062,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) + if (amdgpu_dc_debug_mask & DC_SKIP_DETECTION_LT) + adev->dm.dc->debug.skip_detection_link_training = true; + ++ if (amdgpu_dc_debug_mask & DC_OVERRIDE_PCON_VRR_ID_CHECK) ++ adev->dm.dc->debug.override_pcon_vrr_id_check = true; ++ + adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; + + /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ +@@ -3289,6 +3292,12 @@ static void emulated_link_detect(struct dc_link *link) + break; + } + ++ case SIGNAL_TYPE_HDMI_FRL: { ++ sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; ++ sink_caps.signal = SIGNAL_TYPE_HDMI_FRL; ++ break; ++ } ++ + case SIGNAL_TYPE_DVI_SINGLE_LINK: { + sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; + sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; +@@ -6779,12 +6788,19 @@ static void fill_stream_properties_from_drm_display_mode( + + stream->out_transfer_func.type = TF_TYPE_PREDEFINED; + stream->out_transfer_func.tf = TRANSFER_FUNCTION_SRGB; ++ ++ /* If pixel clock exceeds max HDMI TMDS clock, and FRL is not possible, try ++ * to fall back to 4:2:0 encoding for TMDS ++ */ + if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { + if (!adjust_colour_depth_from_display_info(timing_out, info) && + drm_mode_is_420_also(info, mode_in) && + timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) { +- timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; +- adjust_colour_depth_from_display_info(timing_out, info); ++ if (!stream->link->link_enc->features.flags.bits.IS_HDMI_FRL_CAPABLE || ++ stream->sink->edid_caps.frl_caps.max_rate == 0) { ++ timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; ++ adjust_colour_depth_from_display_info(timing_out, info); ++ } + } + } + +@@ -7383,8 +7399,8 @@ create_stream_for_sink(struct drm_connector *connector, + + update_stream_signal(stream, sink); + +- if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) +- mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket); ++ if (dc_is_hdmi_signal(stream->signal)) ++ mod_build_hf_vsif_infopacket(stream, &stream->hfvsif_infopacket); + + if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || + stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || +@@ -7843,6 +7859,8 @@ amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) + __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); + + new_state->freesync_capable = state->freesync_capable; ++ new_state->freesync_on_desktop_capable = ++ state->freesync_on_desktop_capable; + new_state->abm_level = state->abm_level; + new_state->scaling = state->scaling; + new_state->underscan_enable = state->underscan_enable; +@@ -8555,6 +8573,7 @@ static int to_drm_connector_type(enum signal_type st, uint32_t connector_id) + { + switch (st) { + case SIGNAL_TYPE_HDMI_TYPE_A: ++ case SIGNAL_TYPE_HDMI_FRL: + return DRM_MODE_CONNECTOR_HDMIA; + case SIGNAL_TYPE_EDP: + return DRM_MODE_CONNECTOR_eDP; +@@ -8959,6 +8978,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, + aconnector->audio_inst = -1; + aconnector->pack_sdp_v1_3 = false; + aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; ++ aconnector->hdmi_allm_capable = false; + memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); + mutex_init(&aconnector->hpd_lock); + mutex_init(&aconnector->handle_mst_msg_ready); +@@ -9049,8 +9069,10 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, + connector_type == DRM_MODE_CONNECTOR_eDP) { + drm_connector_attach_hdr_output_metadata_property(&aconnector->base); + +- if (!aconnector->mst_root) ++ if (!aconnector->mst_root) { + drm_connector_attach_vrr_capable_property(&aconnector->base); ++ drm_connector_attach_passive_vrr_capable_property(&aconnector->base); ++ } + + if (adev->dm.hdcp_workqueue) + drm_connector_attach_content_protection_property(&aconnector->base, true); +@@ -9154,6 +9176,10 @@ int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector) + struct drm_device *ddev = aconnector->base.dev; + struct device *hdmi_dev = ddev->dev; + ++ /* ALLM */ ++ drm_connector_attach_allm_capable_property(&aconnector->base); ++ drm_connector_attach_allm_mode_property(&aconnector->base); ++ + if (amdgpu_dc_debug_mask & DC_DISABLE_HDMI_CEC) { + drm_info(ddev, "HDMI-CEC feature masked\n"); + return -EINVAL; +@@ -9621,7 +9647,11 @@ static void update_freesync_state_on_stream( + + aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context; + +- if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) { ++ if (aconn && aconn->as_type == ADAPTIVE_SYNC_TYPE_HDMI) ++ packet_type = PACKET_TYPE_VTEM; ++ ++ else if (aconn && (aconn->as_type == ADAPTIVE_SYNC_TYPE_PCON_ALLOWED || ++ aconn->vsdb_info.replay_mode)) { + pack_sdp_v1_3 = aconn->pack_sdp_v1_3; + + if (aconn->vsdb_info.amd_vsdb_version == 1) +@@ -10840,6 +10870,31 @@ static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_state *state) + return 0; + } + ++static void update_allm_state_on_crtc_stream(struct dm_crtc_state *new_crtc_state, ++ const struct drm_connector_state *new_conn) ++{ ++ struct mod_freesync_config *config = &new_crtc_state->freesync_config; ++ struct dc_stream_state *new_stream = new_crtc_state->stream; ++ bool allm_active = false; ++ ++ switch (new_conn->allm_mode) { ++ case DRM_ALLM_MODE_ENABLED_DYNAMIC: ++ allm_active = config->state == VRR_STATE_ACTIVE_VARIABLE || ++ new_stream->content_type == DISPLAY_CONTENT_TYPE_GAME; ++ break; ++ ++ case DRM_ALLM_MODE_ENABLED_FORCED: ++ allm_active = true; ++ break; ++ ++ case DRM_ALLM_MODE_DISABLED: ++ default: ++ allm_active = false; ++ } ++ ++ new_stream->hdmi_allm_active = allm_active; ++} ++ + /** + * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. + * @state: The atomic state to commit +@@ -10882,12 +10937,14 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) + for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { + struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); + struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); ++ struct amdgpu_dm_connector *dm_conn = to_amdgpu_dm_connector(connector); + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); + struct dc_surface_update *dummy_updates; + struct dc_stream_update stream_update; + struct dc_info_packet hdr_packet; + struct dc_stream_status *status = NULL; + bool abm_changed, hdr_changed, scaling_changed, output_color_space_changed = false; ++ bool allm_changed = false; + + memset(&stream_update, 0, sizeof(stream_update)); + +@@ -10917,7 +10974,11 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) + hdr_changed = + !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); + +- if (!scaling_changed && !abm_changed && !hdr_changed && !output_color_space_changed) ++ allm_changed = dm_conn->hdmi_allm_capable && ++ (new_con_state->allm_mode != old_con_state->allm_mode); ++ ++ if (!scaling_changed && !abm_changed && !hdr_changed && ++ !output_color_space_changed && !allm_changed) + continue; + + stream_update.stream = dm_new_crtc_state->stream; +@@ -10947,6 +11008,17 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) + stream_update.hdr_static_metadata = &hdr_packet; + } + ++ if (allm_changed) { ++ update_allm_state_on_crtc_stream(dm_new_crtc_state, new_con_state); ++ mod_build_hf_vsif_infopacket(dm_new_crtc_state->stream, ++ &dm_new_crtc_state->stream->hfvsif_infopacket); ++ ++ stream_update.hdmi_allm_active = ++ &dm_new_crtc_state->stream->hdmi_allm_active; ++ stream_update.hfvsif_infopacket = ++ &dm_new_crtc_state->stream->hfvsif_infopacket; ++ } ++ + status = dc_stream_get_status(dm_new_crtc_state->stream); + + if (WARN_ON(!status)) +@@ -11326,6 +11398,12 @@ static void get_freesync_config_for_crtc( + config.vsif_supported = true; + config.btr = true; + ++ if (new_con_state->freesync_on_desktop_capable) ++ new_crtc_state->stream->freesync_on_desktop = ++ !new_crtc_state->base.passive_vrr_disabled; ++ else ++ new_crtc_state->stream->freesync_on_desktop = false; ++ + if (fs_vid_mode) { + config.state = VRR_STATE_ACTIVE_FIXED; + config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; +@@ -11337,6 +11415,7 @@ static void get_freesync_config_for_crtc( + } + } else { + config.state = VRR_STATE_UNSUPPORTED; ++ new_crtc_state->stream->freesync_on_desktop = false; + } + out: + new_crtc_state->freesync_config = config; +@@ -13123,8 +13202,8 @@ static void parse_edid_displayid_vrr(struct drm_connector *connector, + } + } + +-static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, +- const struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) ++static int parse_amd_vsdb_did(struct amdgpu_dm_connector *aconnector, ++ const struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) + { + u8 *edid_ext = NULL; + int i; +@@ -13173,13 +13252,13 @@ static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, + return false; + } + +-static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, ++static bool parse_amd_vsdb_cea(struct amdgpu_dm_connector *aconnector, + const struct edid *edid, + struct amdgpu_hdmi_vsdb_info *vsdb_info) + { ++ struct amdgpu_hdmi_vsdb_info vsdb_local = {0}; + u8 *edid_ext = NULL; + int i; +- bool valid_vsdb_found = false; + + /*----- drm_find_cea_extension() -----*/ + /* No EDID or EDID extensions */ +@@ -13200,9 +13279,99 @@ static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, + if (edid_ext[0] != CEA_EXT) + return -ENODEV; + +- valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info); ++ if (!parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, &vsdb_local)) ++ return -ENODEV; ++ ++ *vsdb_info = vsdb_local; ++ return false; ++} ++ ++static bool is_monitor_range_invalid(const struct drm_connector *conn) ++{ ++ return conn->display_info.monitor_range.min_vfreq == 0 || ++ conn->display_info.monitor_range.max_vfreq == 0; ++} ++ ++/* ++ * Returns true if (max_vfreq - min_vfreq) > 10 ++ */ ++static bool is_freesync_capable(const struct drm_monitor_range_info *range) ++{ ++ return (range->max_vfreq - range->min_vfreq) > 10; ++} ++ ++static void monitor_range_from_vsdb(struct drm_display_info *display, ++ const struct amdgpu_hdmi_vsdb_info *vsdb) ++{ ++ display->monitor_range.min_vfreq = vsdb->min_refresh_rate_hz; ++ display->monitor_range.max_vfreq = vsdb->max_refresh_rate_hz; ++} ++ ++/** ++ * Get VRR range from HDMI VRR info in EDID. If VRRmax == 0, ++ * try getting upper bound from AMD vsdb. ++ * ++ * @conn: drm_connector with HDMI VRR info ++ * @vsdb: AMD vsdb from CAE ++ */ ++static void monitor_range_from_hdmi(struct drm_display_info *display, ++ const struct amdgpu_hdmi_vsdb_info *vsdb) ++{ ++ u16 vrr_max = display->hdmi.vrr_cap.vrr_max; ++ ++ /* Try getting upper vrr bound from AMD vsdb */ ++ if (vrr_max == 0) ++ vrr_max = vsdb->max_refresh_rate_hz; ++ ++ /* Use max possible BRR value as a last resort */ ++ if (vrr_max == 0) ++ vrr_max = VTEM_BRR_MAX; ++ ++ display->monitor_range.min_vfreq = display->hdmi.vrr_cap.vrr_min; ++ display->monitor_range.max_vfreq = vrr_max; ++} ++ ++/* ++ * Returns true if connector is capable of freesync ++ * Optionally, can fetch the range from AMD vsdb ++ */ ++static bool copy_range_to_amdgpu_connector(struct drm_connector *conn) ++{ ++ struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); ++ struct drm_monitor_range_info *range = &conn->display_info.monitor_range; ++ ++ aconn->min_vfreq = range->min_vfreq; ++ aconn->max_vfreq = range->max_vfreq; + +- return valid_vsdb_found ? i : -ENODEV; ++ return is_freesync_capable(range); ++} ++ ++static void extend_range_from_vsdb(struct drm_display_info *display, ++ const struct amdgpu_hdmi_vsdb_info *vsdb) ++{ ++ u16 vrr_min = display->monitor_range.min_vfreq; ++ u16 vrr_max = display->monitor_range.max_vfreq; ++ ++ /* Always extend upper limit */ ++ if (vsdb->max_refresh_rate_hz > vrr_max) ++ vrr_max = vsdb->max_refresh_rate_hz; ++ ++ /* ++ * Only extend lower limit if current one disables LFC. ++ ++ * During widespread testing, we found that some manufacturers probably ++ * had issues with their monitors' lower VRR boundaries and adjusted ++ * them up (Gigabyte X34GS with official range 48 - 180, AMD vsdb 48 - ++ * 180 yet Monitor Ranges 55 - 180). After setting the lower boundary ++ * from AMD vsdb, such monitors start having blanking issues. ++ * ++ * Work around that by not touching VRR min if it still supports LFC. ++ */ ++ if (vsdb->min_refresh_rate_hz < vrr_min && (vrr_min * 2 >= vrr_max)) ++ vrr_min = vsdb->min_refresh_rate_hz; ++ ++ display->monitor_range.min_vfreq = vrr_min; ++ display->monitor_range.max_vfreq = vrr_max; + } + + /** +@@ -13219,16 +13388,20 @@ static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, + void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, + const struct drm_edid *drm_edid) + { +- int i = 0; + struct amdgpu_dm_connector *amdgpu_dm_connector = + to_amdgpu_dm_connector(connector); + struct dm_connector_state *dm_con_state = NULL; + struct dc_sink *sink; + struct amdgpu_device *adev = drm_to_adev(connector->dev); + struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; ++ struct amdgpu_hdmi_vsdb_info vsdb_did = {0}; ++ struct drm_hdmi_vrr_cap hdmi_vrr = {0}; ++ struct dpcd_caps dpcd_caps = {0}; + const struct edid *edid; ++ bool freesync_on_desktop = false; + bool freesync_capable = false; +- enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; ++ bool pcon_allowed = false; ++ bool is_pcon = false; + + if (!connector->state) { + drm_err(adev_to_drm(adev), "%s - Connector has no state", __func__); +@@ -13256,68 +13429,77 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, + if (!adev->dm.freesync_module || !dc_supports_vrr(sink->ctx->dce_version)) + goto update; + ++ /* Gather all data */ + edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw() ++ parse_amd_vsdb_cea(amdgpu_dm_connector, edid, &vsdb_info); ++ hdmi_vrr = connector->display_info.hdmi.vrr_cap; ++ ++ if (amdgpu_dm_connector->dc_link) { ++ dpcd_caps = amdgpu_dm_connector->dc_link->dpcd_caps; ++ is_pcon = dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER; ++ pcon_allowed = dm_helpers_is_vrr_pcon_allowed( ++ amdgpu_dm_connector->dc_link, connector->dev); ++ } ++ ++ /* DP & eDP excluding PCONs */ ++ if ((sink->sink_signal == SIGNAL_TYPE_EDP || ++ sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) && !is_pcon) { ++ /* Some eDP panels only have the refresh rate range info in DisplayID */ ++ if (is_monitor_range_invalid(connector)) ++ parse_edid_displayid_vrr(connector, edid); ++ /* ++ * Many monitors expose AMD vsdb in CAE even for DP and their ++ * monitor ranges do not contain Range Limits Only flag ++ */ ++ if (is_monitor_range_invalid(connector)) ++ monitor_range_from_vsdb(&connector->display_info, &vsdb_info); + +- /* Some eDP panels only have the refresh rate range info in DisplayID */ +- if ((connector->display_info.monitor_range.min_vfreq == 0 || +- connector->display_info.monitor_range.max_vfreq == 0)) +- parse_edid_displayid_vrr(connector, edid); +- +- if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || +- sink->sink_signal == SIGNAL_TYPE_EDP)) { +- if (amdgpu_dm_connector->dc_link && +- amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param) { +- amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq; +- amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq; +- if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) +- freesync_capable = true; +- } ++ /* Try extending range if found in AMD vsdb */ ++ extend_range_from_vsdb(&connector->display_info, &vsdb_info); + +- parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); ++ if (dpcd_caps.allow_invalid_MSA_timing_param) ++ freesync_capable = copy_range_to_amdgpu_connector(connector); + +- if (vsdb_info.replay_mode) { +- amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode; +- amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version; ++ /* eDP */ ++ parse_amd_vsdb_did(amdgpu_dm_connector, edid, &vsdb_did); ++ if (vsdb_did.replay_mode) { ++ amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_did.replay_mode; ++ amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_did.amd_vsdb_version; + amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP; + } + +- } else if (drm_edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { +- i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); +- if (i >= 0 && vsdb_info.freesync_supported) { +- amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; +- amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; +- if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) +- freesync_capable = true; +- +- connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; +- connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; +- } +- } +- +- if (amdgpu_dm_connector->dc_link) +- as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link); +- +- if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) { +- i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); +- if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) { +- +- amdgpu_dm_connector->pack_sdp_v1_3 = true; +- amdgpu_dm_connector->as_type = as_type; ++ /* HDMI */ ++ } else if (dc_is_hdmi_signal(sink->sink_signal)) { ++ /* Prefer HDMI VRR */ ++ if (hdmi_vrr.supported) { ++ amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_HDMI; ++ monitor_range_from_hdmi(&connector->display_info, &vsdb_info); ++ } else if (vsdb_info.freesync_supported) ++ monitor_range_from_vsdb(&connector->display_info, &vsdb_info); ++ ++ freesync_capable = copy_range_to_amdgpu_connector(connector); ++ freesync_on_desktop = freesync_capable; ++ ++ /* DP -> HDMI PCON */ ++ } else if (pcon_allowed) { ++ /* Prefer HDMI VRR */ ++ if (hdmi_vrr.supported) ++ monitor_range_from_hdmi(&connector->display_info, &vsdb_info); ++ else if (vsdb_info.freesync_supported) { + amdgpu_dm_connector->vsdb_info = vsdb_info; +- +- amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; +- amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; +- if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) +- freesync_capable = true; +- +- connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; +- connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; ++ monitor_range_from_vsdb(&connector->display_info, &vsdb_info); + } ++ ++ amdgpu_dm_connector->pack_sdp_v1_3 = true; ++ amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_PCON_ALLOWED; ++ freesync_capable = copy_range_to_amdgpu_connector(connector); + } + + update: +- if (dm_con_state) ++ if (dm_con_state) { + dm_con_state->freesync_capable = freesync_capable; ++ dm_con_state->freesync_on_desktop_capable = freesync_on_desktop; ++ } + + if (connector->state && amdgpu_dm_connector->dc_link && !freesync_capable && + amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported) { +@@ -13326,8 +13508,15 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, + } + + if (connector->vrr_capable_property) +- drm_connector_set_vrr_capable_property(connector, +- freesync_capable); ++ drm_connector_set_vrr_capable_property(connector, freesync_capable); ++ ++ if (connector->passive_vrr_capable_property) ++ drm_connector_set_passive_vrr_capable_property(connector, freesync_on_desktop); ++ ++ amdgpu_dm_connector->hdmi_allm_capable = connector->display_info.hdmi.allm; ++ if (connector->allm_capable_property) ++ drm_connector_set_allm_capable_property( ++ connector, connector->display_info.hdmi.allm); + } + + void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +index 800813671748..b9d27a483b1e 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +@@ -847,6 +847,9 @@ struct amdgpu_dm_connector { + unsigned int hdmi_hpd_debounce_delay_ms; + struct delayed_work hdmi_hpd_debounce_work; + struct dc_sink *hdmi_prev_sink; ++ ++ /* HDMI ALLM */ ++ bool hdmi_allm_capable; + }; + + static inline void amdgpu_dm_set_mst_status(uint8_t *status, +@@ -1020,6 +1023,7 @@ struct dm_connector_state { + uint8_t underscan_hborder; + bool underscan_enable; + bool freesync_capable; ++ bool freesync_on_desktop_capable; + bool update_hdcp; + bool abm_sysfs_forbidden; + uint8_t abm_level; +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +index 1f41d6540b83..63d654c9128a 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +@@ -137,7 +137,12 @@ enum dc_edid_status dm_helpers_parse_edid_caps( + edid_caps->display_name, + AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); + +- edid_caps->edid_hdmi = connector->display_info.is_hdmi; ++ if (connector->display_info.is_hdmi) { ++ edid_caps->edid_hdmi = true; ++ edid_caps->allm = connector->display_info.hdmi.allm; ++ edid_caps->fva = connector->display_info.hdmi.vrr_cap.fva; ++ edid_caps->hdmi_vrr = connector->display_info.hdmi.vrr_cap.supported; ++ } + + if (edid_caps->edid_hdmi) + populate_hdmi_info_from_connector(&connector->display_info.hdmi, edid_caps); +@@ -995,7 +1000,32 @@ dm_helpers_read_acpi_edid(struct amdgpu_dm_connector *aconnector) + + void populate_hdmi_info_from_connector(struct drm_hdmi_info *hdmi, struct dc_edid_caps *edid_caps) + { ++ struct dc_hdmi_dsc_caps *dsc = &edid_caps->dsc_caps; ++ + edid_caps->scdc_present = hdmi->scdc.supported; ++ ++ /* FRL */ ++ if (hdmi->frl_cap.max_rate == 0) ++ return; ++ ++ edid_caps->frl_caps.max_rate = hdmi->frl_cap.max_rate; ++ edid_caps->frl_caps.max_lanes = hdmi->frl_cap.max_lanes; ++ edid_caps->frl_caps.max_rate_per_lane = hdmi->frl_cap.max_rate_per_lane; ++ ++ /* DSC */ ++ if (hdmi->dsc_cap.v_1p2 != true) ++ return; ++ ++ dsc->v1p2 = hdmi->dsc_cap.v_1p2; ++ dsc->all_bpp = hdmi->dsc_cap.all_bpp; ++ dsc->native_420 = hdmi->dsc_cap.native_420; ++ dsc->max_bpc = hdmi->dsc_cap.bpc_supported; ++ dsc->max_slices = hdmi->dsc_cap.max_slices; ++ dsc->total_chunk_kbytes = hdmi->dsc_cap.total_chunk_kbytes; ++ ++ dsc->frl.max_rate = hdmi->dsc_cap.frl_cap.max_rate; ++ dsc->frl.max_lanes = hdmi->dsc_cap.frl_cap.max_lanes; ++ dsc->frl.max_rate_per_lane = hdmi->dsc_cap.frl_cap.max_rate_per_lane; + } + + enum dc_edid_status dm_helpers_read_local_edid( +@@ -1381,40 +1411,32 @@ void dm_helpers_dp_mst_update_branch_bandwidth( + // TODO + } + +-static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id) ++bool dm_helpers_is_vrr_pcon_allowed(const struct dc_link *link, const struct drm_device *dev) + { +- bool ret_val = false; ++ if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER) ++ return false; ++ ++ if (!link->dpcd_caps.allow_invalid_MSA_timing_param) ++ return false; ++ ++ if (!link->dpcd_caps.adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT) ++ return false; + +- switch (branch_dev_id) { ++ switch (link->dpcd_caps.branch_dev_id) { + case DP_BRANCH_DEVICE_ID_0060AD: + case DP_BRANCH_DEVICE_ID_00E04C: + case DP_BRANCH_DEVICE_ID_90CC24: +- ret_val = true; +- break; +- default: +- break; ++ case DP_BRANCH_DEVICE_ID_2B02F0: ++ return true; + } + +- return ret_val; +-} +- +-enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link) +-{ +- struct dpcd_caps *dpcd_caps = &link->dpcd_caps; +- enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; +- +- switch (dpcd_caps->dongle_type) { +- case DISPLAY_DONGLE_DP_HDMI_CONVERTER: +- if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true && +- dpcd_caps->allow_invalid_MSA_timing_param == true && +- dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id)) +- as_type = FREESYNC_TYPE_PCON_IN_WHITELIST; +- break; +- default: +- break; ++ if (link->dc->debug.override_pcon_vrr_id_check) { ++ drm_info(dev, "Overriding VRR PCON check for ID: 0x%06x\n", ++ link->dpcd_caps.branch_dev_id); ++ return true; + } + +- return as_type; ++ return false; + } + + bool dm_helpers_is_fullscreen(struct dc_context *ctx, struct dc_stream_state *stream) +diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c +index 268e2414b34f..42e3aa3a8709 100644 +--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c ++++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c +@@ -177,6 +177,8 @@ uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom2( + return ATOM_ENCODER_MODE_DVI; + case SIGNAL_TYPE_HDMI_TYPE_A: + return ATOM_ENCODER_MODE_HDMI; ++ case SIGNAL_TYPE_HDMI_FRL: ++ return ATOM_ENCODER_MODE_HDMI_FRL; + case SIGNAL_TYPE_LVDS: + return ATOM_ENCODER_MODE_LVDS; + case SIGNAL_TYPE_EDP: +diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c +index 349f0e5d5856..b2d9ae570b18 100644 +--- a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c ++++ b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c +@@ -49,6 +49,9 @@ static uint8_t signal_type_to_atom_dig_mode(enum signal_type s) + case SIGNAL_TYPE_HDMI_TYPE_A: + atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_HDMI; + break; ++ case SIGNAL_TYPE_HDMI_FRL: ++ atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_HDMI_FRL; ++ break; + case SIGNAL_TYPE_DISPLAY_PORT_MST: + atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP_MST; + break; +diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c +index 1a5fefcde8af..2357ed6b8752 100644 +--- a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c ++++ b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c +@@ -47,6 +47,9 @@ static uint8_t signal_type_to_atom_dig_mode(enum signal_type s) + case SIGNAL_TYPE_HDMI_TYPE_A: + atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_HDMI; + break; ++ case SIGNAL_TYPE_HDMI_FRL: ++ atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_HDMI_FRL; ++ break; + case SIGNAL_TYPE_DISPLAY_PORT_MST: + atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP_MST; + break; +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +index 72558cc55a9a..afc4bc30d214 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +@@ -231,13 +231,16 @@ static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state * + + if (old_pipe->stream && new_pipe->stream && old_pipe->stream == new_pipe->stream) { + has_active_hpo = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(old_pipe) && +- dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe); ++ dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe); + ++ has_active_hpo |= dc_is_hdmi_frl_signal(old_pipe->stream->signal) && ++ dc_is_hdmi_frl_signal(new_pipe->stream->signal); + } + + if (!has_active_hpo && !stream_changed_otg_dig_on && pipe->stream && + (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) || !pipe_link_enc) && +- !dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe)) { ++ !dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe) && ++ !dc_is_hdmi_frl_signal(pipe->stream->signal)) { + /* This w/a should not trigger when we have a dig active */ + if (disable) { + if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc) +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index cb85b7ac2697..1cca1f0c1aa2 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -1528,6 +1528,9 @@ struct dc *dc_create(const struct dc_init_data *init_params) + } + + dc->dcn_reg_offsets = init_params->dcn_reg_offsets; ++ DC_LOG_ERROR("DCN reg offset 1: 0x%x\n", init_params->dcn_reg_offsets[1]); ++ DC_LOG_ERROR("DCN reg offset 2: 0x%x\n", init_params->dcn_reg_offsets[2]); ++ DC_LOG_ERROR("DCN reg offset 3: 0x%x\n", init_params->dcn_reg_offsets[3]); + dc->nbio_reg_offsets = init_params->nbio_reg_offsets; + dc->clk_reg_offsets = init_params->clk_reg_offsets; + +@@ -3292,6 +3295,9 @@ static void copy_stream_update_to_stream(struct dc *dc, + if (update->vrr_active_fixed) + stream->vrr_active_fixed = *update->vrr_active_fixed; + ++ if (update->hdmi_allm_active) ++ stream->hdmi_allm_active = *update->hdmi_allm_active; ++ + if (update->crtc_timing_adjust) { + if (stream->adjust.v_total_min != update->crtc_timing_adjust->v_total_min || + stream->adjust.v_total_max != update->crtc_timing_adjust->v_total_max || +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +index bbce751b485f..b08362afbd76 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +@@ -270,6 +270,8 @@ char *dc_status_to_str(enum dc_status status) + return "HW Cursor not supported"; + case DC_FAIL_DP_TUNNEL_BW_VALIDATE: + return "Fail DP Tunnel BW validation"; ++ case DC_FAIL_FRL_LINK_BANDWIDTH: ++ return "Insufficient FRL link bandwidth"; + case DC_ERROR_UNEXPECTED: + return "Unexpected error"; + } +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c +index 7bb4504889be..01233ccfd5ae 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c +@@ -345,6 +345,10 @@ enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc + DP_128b_132b_ENCODING) + return DC_LINK_ENCODING_DP_128b_132b; + } else if (dc_is_hdmi_signal(link->connector_signal)) { ++ if (link->local_sink->edid_caps.frl_caps.max_rate > 0) ++ return DC_LINK_ENCODING_HDMI_FRL; ++ else ++ return DC_LINK_ENCODING_HDMI_TMDS; + } + + return DC_LINK_ENCODING_UNSPECIFIED; +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +index 848c267ef11e..beeaeae4810e 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +@@ -48,10 +48,13 @@ + #include "virtual/virtual_link_hwss.h" + #include "link/hwss/link_hwss_dio.h" + #include "link/hwss/link_hwss_dpia.h" ++#include "link/hwss/link_hwss_hpo_frl.h" + #include "link/hwss/link_hwss_hpo_dp.h" + #include "link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h" + #include "link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h" + ++#include "link/protocols/link_frl_training.h" ++ + #if defined(CONFIG_DRM_AMD_DC_SI) + #include "dce60/dce60_resource.h" + #endif +@@ -511,6 +514,27 @@ bool resource_construct( + } + } + ++ pool->hpo_hdmi_stream_enc_count = 0; ++ if (create_funcs->create_hpo_hdmi_stream_encoder) { ++ for (i = 0; i < caps->num_hpo_hdmi_stream_encoder; i++) { ++ pool->hpo_hdmi_stream_enc[i] = create_funcs->create_hpo_hdmi_stream_encoder(i+ENGINE_ID_HPO_0, ctx); ++ if (pool->hpo_hdmi_stream_enc[i] == NULL) ++ DC_ERR("DC: failed to create HPO HDMI stream encoder!\n"); ++ pool->hpo_hdmi_stream_enc_count++; ++ ++ } ++ } ++ ++ pool->hpo_hdmi_link_enc_count = 0; ++ if (create_funcs->create_hpo_hdmi_link_encoder) { ++ for (i = 0; i < caps->num_hpo_hdmi_link_encoder; i++) { ++ pool->hpo_hdmi_link_enc[i] = create_funcs->create_hpo_hdmi_link_encoder(i, ctx); ++ if (pool->hpo_hdmi_link_enc[i] == NULL) ++ DC_ERR("DC: failed to create HPO HDMI link encoder!\n"); ++ pool->hpo_hdmi_link_enc_count++; ++ } ++ } ++ + for (i = 0; i < caps->num_mpc_3dlut; i++) { + pool->mpc_lut[i] = dc_create_3dlut_func(); + if (pool->mpc_lut[i] == NULL) +@@ -4033,6 +4057,15 @@ enum dc_status resource_map_pool_resources( + } + } + ++ if (dc_is_hdmi_frl_signal(stream->signal)) { ++ if (!hdmi_decide_link_settings(stream, pipe_ctx)) ++ return DC_FAIL_FRL_LINK_BANDWIDTH; ++ ++ /* Only one pair of encoders on all HW so far. */ ++ pipe_ctx->stream_res.hpo_hdmi_stream_enc = pool->hpo_hdmi_stream_enc[0]; ++ pipe_ctx->link_res.hpo_hdmi_link_enc = pool->hpo_hdmi_link_enc[0]; ++ } ++ + if (dc->config.unify_link_enc_assignment && is_dio_encoder) + if (!add_dio_link_enc_to_ctx(dc, context, pool, pipe_ctx, stream)) + return DC_NO_LINK_ENC_RESOURCE; +@@ -4659,7 +4692,7 @@ static void set_avi_info_frame( + vic = 0; + format = stream->timing.timing_3d_format; + /*todo, add 3DStereo support*/ +- if (format != TIMING_3D_FORMAT_NONE) { ++ if (format != TIMING_3D_FORMAT_NONE || stream->hdmi_allm_active) { + // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled + switch (pipe_ctx->stream->timing.hdmi_vic) { + case 1: +@@ -5484,6 +5517,8 @@ const struct link_hwss *get_link_hwss(const struct dc_link *link, + */ + return (requires_fixed_vs_pe_retimer_hpo_link_hwss(link) ? + get_hpo_fixed_vs_pe_retimer_dp_link_hwss() : get_hpo_dp_link_hwss()); ++ else if (can_use_hpo_hdmi_frl_link_hwss(link, link_res)) ++ return get_hpo_hdmi_frl_link_hwss(); + else if (can_use_dpia_link_hwss(link, link_res)) + return get_dpia_link_hwss(); + else if (can_use_dio_link_hwss(link, link_res)) +@@ -5711,5 +5746,5 @@ bool resource_is_hpo_acquired(struct dc_state *context) + } + } + +- return false; ++ return true; + } +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +index f59020f1a722..cd7d6f5c9c0f 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +@@ -52,6 +52,11 @@ void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink) + else + stream->signal = sink->sink_signal; + ++ if (dc_is_hdmi_tmds_signal(stream->signal)) ++ if (stream->link->link_enc->features.flags.bits.IS_HDMI_FRL_CAPABLE && ++ sink->edid_caps.frl_caps.max_rate > 0) ++ stream->signal = SIGNAL_TYPE_HDMI_FRL; ++ + if (dc_is_dvi_signal(stream->signal)) { + if (stream->ctx->dc->caps.dual_link_dvi && + (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK && +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index ab19b6230945..7b22575ff638 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -1057,6 +1057,7 @@ struct dc_debug_options { + bool scl_reset_length10; + bool hdmi20_disable; + bool skip_detection_link_training; ++ bool override_pcon_vrr_id_check; + uint32_t edid_read_retry_times; + unsigned int force_odm_combine; //bit vector based on otg inst + unsigned int seamless_boot_odm_combine; +diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +index 5e3646b7550c..f4f1e9f3e6d5 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +@@ -157,6 +157,7 @@ struct dc_link_settings { + enum dc_link_spread link_spread; + bool use_link_rate_set; + uint8_t link_rate_set; ++ uint8_t frl_rate; + }; + + struct dc_tunnel_settings { +diff --git a/drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h b/drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h +index fcd3ab4b0045..ef779ba1c14c 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h +@@ -64,7 +64,8 @@ struct dp_hdmi_dongle_signature_data { + #define HDMI_SCDC_CONFIG_0 0x30 + #define HDMI_SCDC_CONFIG_1 0x31 + #define HDMI_SCDC_SOURCE_TEST_REQ 0x35 +-#define HDMI_SCDC_STATUS_FLAGS 0x40 ++#define HDMI_SCDC_STATUS_FLAGS_0 0x40 ++#define HDMI_SCDC_STATUS_FLAGS_1 0x41 + #define HDMI_SCDC_ERR_DETECT 0x50 + #define HDMI_SCDC_TEST_CONFIG 0xC0 + +diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h +index 719b98d8e8ca..dc181854386f 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h +@@ -242,6 +242,7 @@ struct dc_stream_state { + bool vrr_active_variable; + bool freesync_on_desktop; + bool vrr_active_fixed; ++ bool hdmi_allm_active; + + bool converter_disable_audio; + uint8_t qs_bit; +@@ -345,6 +346,7 @@ struct dc_stream_update { + bool *allow_freesync; + bool *vrr_active_variable; + bool *vrr_active_fixed; ++ bool *hdmi_allm_active; + + struct colorspace_transform *gamut_remap; + enum dc_color_space *output_color_space; +diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h +index 0e953059ff6d..2b90eb174d77 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_types.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h +@@ -185,6 +185,41 @@ struct dc_panel_patch { + unsigned int wait_after_dpcd_poweroff_ms; + }; + ++/** ++ * struct dc_hdmi_frl_caps - HDMI FRL Capabilities read from EDID. ++ */ ++struct dc_hdmi_frl_caps { ++ /* raw max_rate field */ ++ uint8_t max_rate; ++ ++ /* max supported data rate per lane in Gbps */ ++ uint8_t max_rate_per_lane; ++ ++ /* max supported FRL lanes by sink */ ++ uint8_t max_lanes; ++}; ++ ++/** ++ * struct dc_hdmi_dsc_caps - HDMI DSC Capabilities read from EDID. ++ */ ++struct dc_hdmi_dsc_caps { ++ /* Support DSC v1.2 */ ++ bool v1p2; ++ ++ bool all_bpp; ++ bool native_420; ++ ++ uint8_t max_bpc; ++ uint8_t total_chunk_kbytes; ++ uint8_t max_slices; ++ ++ /* max supported pixel clock per slice in MHz */ ++ uint16_t max_clk; ++ ++ /* Alternative FRL caps to use with DSC */ ++ struct dc_hdmi_frl_caps frl; ++}; ++ + /** + * struct dc_edid_caps - Capabilities read from EDID. + * @analog: Whether the monitor is analog. Used by DVI-I handling. +@@ -210,9 +245,16 @@ struct dc_edid_caps { + + uint32_t max_tmds_clk_mhz; + +- /*HDMI 2.0 caps*/ ++ /* HDMI 2.0 caps */ + bool lte_340mcsc_scramble; + ++ /* HDMI 2.1 caps */ ++ struct dc_hdmi_frl_caps frl_caps; ++ struct dc_hdmi_dsc_caps dsc_caps; ++ bool allm; ++ bool fva; ++ bool hdmi_vrr; ++ + bool edid_hdmi; + bool hdr_supported; + bool rr_capable; +diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c +index 97df04b7e39d..13383f2b68ff 100644 +--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c ++++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c +@@ -170,6 +170,59 @@ void dccg31_set_dpstreamclk( + dccg31_enable_dpstreamclk(dccg, otg_inst); + } + ++static void dccg31_enable_hdmistreamclk(struct dccg *dccg, int otg_inst, int hdmi_hpo_inst) ++{ ++ struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); ++ ++ /* enabled to select one of the DTBCLKs for pipe */ ++ switch (hdmi_hpo_inst) { ++ case 0: ++ if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream) { ++ REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, ++ HDMISTREAMCLK0_GATE_DISABLE, 1); ++ } ++ REG_UPDATE_2(HDMISTREAMCLK_CNTL, ++ HDMISTREAMCLK0_SRC_SEL, otg_inst, ++ HDMISTREAMCLK0_EN, 1); ++ break; ++ default: ++ BREAK_TO_DEBUGGER(); ++ return; ++ } ++} ++ ++static void dccg31_disable_hdmistreamclk(struct dccg *dccg, int hdmi_hpo_inst) ++{ ++ struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); ++ ++ switch (hdmi_hpo_inst) { ++ case 0: ++ REG_UPDATE(HDMISTREAMCLK_CNTL, ++ HDMISTREAMCLK0_EN, 0); ++ if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream) { ++ REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, ++ HDMISTREAMCLK0_GATE_DISABLE, 0); ++ } ++ break; ++ default: ++ BREAK_TO_DEBUGGER(); ++ return; ++ } ++} ++ ++static void dccg31_set_hdmistreamclk( ++ struct dccg *dccg, ++ enum streamclk_source src, ++ int otg_inst, ++ int hdmi_hpo_inst) ++{ ++ /* enabled to select one of the DTBCLKs for pipe */ ++ if (src == REFCLK) ++ dccg31_disable_hdmistreamclk(dccg, hdmi_hpo_inst); ++ else ++ dccg31_enable_hdmistreamclk(dccg, otg_inst, hdmi_hpo_inst); ++} ++ + void dccg31_enable_symclk32_se( + struct dccg *dccg, + int hpo_se_inst, +@@ -836,6 +889,7 @@ static const struct dccg_funcs dccg31_funcs = { + .get_dccg_ref_freq = dccg31_get_dccg_ref_freq, + .dccg_init = dccg31_init, + .set_dpstreamclk = dccg31_set_dpstreamclk, ++ .set_hdmistreamclk = dccg31_set_hdmistreamclk, + .enable_symclk32_se = dccg31_enable_symclk32_se, + .disable_symclk32_se = dccg31_disable_symclk32_se, + .enable_symclk32_le = dccg31_enable_symclk32_le, +diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h +index bf659920d4cc..4d6753ade738 100644 +--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h ++++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h +@@ -147,6 +147,7 @@ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_GATE_DISABLE, mask_sh),\ ++ DCCG_SF(DCCG_GATE_DISABLE_CNTL3, HDMISTREAMCLK0_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\ +diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c +index ef3db6beba25..a183950fbdd3 100644 +--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c ++++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c +@@ -285,6 +285,59 @@ void dccg314_set_dpstreamclk( + } + } + ++static void dccg314_enable_hdmistreamclk(struct dccg *dccg, int otg_inst, int hdmi_hpo_inst) ++{ ++ struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); ++ ++ /* enabled to select one of the DTBCLKs for pipe */ ++ switch (hdmi_hpo_inst) { ++ case 0: ++ if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream) { ++ REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, ++ HDMISTREAMCLK0_GATE_DISABLE, 1); ++ } ++ REG_UPDATE_2(HDMISTREAMCLK_CNTL, ++ HDMISTREAMCLK0_SRC_SEL, otg_inst, ++ HDMISTREAMCLK0_EN, 1); ++ break; ++ default: ++ BREAK_TO_DEBUGGER(); ++ return; ++ } ++} ++ ++static void dccg314_disable_hdmistreamclk(struct dccg *dccg, int hdmi_hpo_inst) ++{ ++ struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); ++ ++ switch (hdmi_hpo_inst) { ++ case 0: ++ REG_UPDATE(HDMISTREAMCLK_CNTL, ++ HDMISTREAMCLK0_EN, 0); ++ if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream) { ++ REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, ++ HDMISTREAMCLK0_GATE_DISABLE, 0); ++ } ++ break; ++ default: ++ BREAK_TO_DEBUGGER(); ++ return; ++ } ++} ++ ++void dccg314_set_hdmistreamclk( ++ struct dccg *dccg, ++ enum streamclk_source src, ++ int otg_inst, ++ int hdmi_hpo_inst) ++{ ++ /* enabled to select one of the DTBCLKs for pipe */ ++ if (src == REFCLK) ++ dccg314_disable_hdmistreamclk(dccg, hdmi_hpo_inst); ++ else ++ dccg314_enable_hdmistreamclk(dccg, otg_inst, hdmi_hpo_inst); ++} ++ + static void dccg314_init(struct dccg *dccg) + { + int otg_inst; +@@ -359,6 +412,7 @@ static const struct dccg_funcs dccg314_funcs = { + .get_dccg_ref_freq = dccg31_get_dccg_ref_freq, + .dccg_init = dccg314_init, + .set_dpstreamclk = dccg314_set_dpstreamclk, ++ .set_hdmistreamclk = dccg314_set_hdmistreamclk, + .enable_symclk32_se = dccg31_enable_symclk32_se, + .disable_symclk32_se = dccg31_disable_symclk32_se, + .enable_symclk32_le = dccg31_enable_symclk32_le, +diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h +index a609635f35db..b38dcdcd854c 100644 +--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h ++++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h +@@ -151,6 +151,7 @@ + DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_MODULO, mask_sh),\ + DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_PHASE, mask_sh),\ + DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_MODULO, mask_sh),\ ++ DCCG_SF(DCCG_GATE_DISABLE_CNTL3, HDMISTREAMCLK0_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\ +@@ -208,4 +209,10 @@ void dccg314_set_dpstreamclk( + int otg_inst, + int dp_hpo_inst); + ++void dccg314_set_hdmistreamclk( ++ struct dccg *dccg, ++ enum streamclk_source src, ++ int otg_inst, ++ int hdmi_hpo_inst); ++ + #endif //__DCN314_DCCG_H__ +diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c +index 21a6ca5ca192..3db490280f09 100644 +--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c ++++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c +@@ -309,6 +309,51 @@ static void dccg32_set_dpstreamclk( + } + } + ++static void dccg32_enable_hdmistreamclk(struct dccg *dccg, int otg_inst, int hdmi_hpo_inst) ++{ ++ struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); ++ ++ /* enabled to select one of the DTBCLKs for pipe */ ++ switch (hdmi_hpo_inst) { ++ case 0: ++ REG_UPDATE_2(HDMISTREAMCLK_CNTL, ++ HDMISTREAMCLK0_SRC_SEL, otg_inst, ++ HDMISTREAMCLK0_EN, 1); ++ break; ++ default: ++ BREAK_TO_DEBUGGER(); ++ return; ++ } ++} ++ ++static void dccg32_disable_hdmistreamclk(struct dccg *dccg, int hdmi_hpo_inst) ++{ ++ struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); ++ ++ switch (hdmi_hpo_inst) { ++ case 0: ++ REG_UPDATE(HDMISTREAMCLK_CNTL, ++ HDMISTREAMCLK0_EN, 0); ++ break; ++ default: ++ BREAK_TO_DEBUGGER(); ++ return; ++ } ++} ++ ++static void dccg32_set_hdmistreamclk( ++ struct dccg *dccg, ++ enum streamclk_source src, ++ int otg_inst, ++ int hdmi_hpo_inst) ++{ ++ /* enabled to select one of the DTBCLKs for pipe */ ++ if (src == REFCLK) ++ dccg32_disable_hdmistreamclk(dccg, hdmi_hpo_inst); ++ else ++ dccg32_enable_hdmistreamclk(dccg, otg_inst, hdmi_hpo_inst); ++} ++ + static void dccg32_otg_add_pixel(struct dccg *dccg, + uint32_t otg_inst) + { +@@ -332,6 +377,7 @@ static const struct dccg_funcs dccg32_funcs = { + .get_dccg_ref_freq = dccg32_get_dccg_ref_freq, + .dccg_init = dccg31_init, + .set_dpstreamclk = dccg32_set_dpstreamclk, ++ .set_hdmistreamclk = dccg32_set_hdmistreamclk, + .enable_symclk32_se = dccg31_enable_symclk32_se, + .disable_symclk32_se = dccg31_disable_symclk32_se, + .enable_symclk32_le = dccg31_enable_symclk32_le, +diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +index bd2f528137b2..9224645eaf8d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c ++++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +@@ -2155,6 +2155,63 @@ static void dccg35_set_dpstreamclk_root_clock_gating_cb( + dccg35_disable_dpstreamclk_new(dccg, dp_hpo_inst); + } + ++static void dccg35_enable_hdmistreamclk(struct dccg *dccg, int otg_inst, int hdmi_hpo_inst) ++{ ++ struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); ++ ++ /* enabled to select one of the DTBCLKs for pipe */ ++ switch (hdmi_hpo_inst) { ++ case 0: ++ if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream) { ++ REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, ++ HDMISTREAMCLK0_ROOT_GATE_DISABLE, 1); ++ REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, ++ HDMISTREAMCLK0_GATE_DISABLE, 1); ++ } ++ REG_UPDATE_2(HDMISTREAMCLK_CNTL, ++ HDMISTREAMCLK0_SRC_SEL, otg_inst, ++ HDMISTREAMCLK0_EN, 1); ++ break; ++ default: ++ BREAK_TO_DEBUGGER(); ++ return; ++ } ++} ++ ++static void dccg35_disable_hdmistreamclk(struct dccg *dccg, int hdmi_hpo_inst) ++{ ++ struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); ++ ++ switch (hdmi_hpo_inst) { ++ case 0: ++ REG_UPDATE(HDMISTREAMCLK_CNTL, ++ HDMISTREAMCLK0_EN, 0); ++ if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream) { ++ REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, ++ HDMISTREAMCLK0_ROOT_GATE_DISABLE, 0); ++ REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, ++ HDMISTREAMCLK0_GATE_DISABLE, 0); ++ } ++ break; ++ default: ++ BREAK_TO_DEBUGGER(); ++ return; ++ } ++} ++ ++static void dccg35_set_hdmistreamclk( ++ struct dccg *dccg, ++ enum streamclk_source src, ++ int otg_inst, ++ int hdmi_hpo_inst) ++{ ++ /* enabled to select one of the DTBCLKs for pipe */ ++ if (src == REFCLK) ++ dccg35_disable_hdmistreamclk(dccg, hdmi_hpo_inst); ++ else ++ dccg35_enable_hdmistreamclk(dccg, otg_inst, hdmi_hpo_inst); ++} ++ + static void dccg35_update_dpp_dto_cb(struct dccg *dccg, int dpp_inst, + int req_dppclk) + { +@@ -2398,6 +2455,7 @@ static const struct dccg_funcs dccg35_funcs_new = { + .get_dccg_ref_freq = dccg31_get_dccg_ref_freq, + .dccg_init = dccg35_init_cb, + .set_dpstreamclk = dccg35_set_dpstreamclk_cb, ++ .set_hdmistreamclk = dccg35_set_hdmistreamclk, + .set_dpstreamclk_root_clock_gating = dccg35_set_dpstreamclk_root_clock_gating_cb, + .enable_symclk32_se = dccg35_enable_symclk32_se_cb, + .disable_symclk32_se = dccg35_disable_symclk32_se_cb, +@@ -2429,6 +2487,7 @@ static const struct dccg_funcs dccg35_funcs = { + .get_dccg_ref_freq = dccg31_get_dccg_ref_freq, + .dccg_init = dccg35_init, + .set_dpstreamclk = dccg35_set_dpstreamclk, ++ .set_hdmistreamclk = dccg35_set_hdmistreamclk, + .set_dpstreamclk_root_clock_gating = dccg35_set_dpstreamclk_root_clock_gating, + .enable_symclk32_se = dccg31_enable_symclk32_se, + .disable_symclk32_se = dccg35_disable_symclk32_se, +diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c +index 663a18ee5162..f176100ea198 100644 +--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c ++++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c +@@ -587,6 +587,63 @@ void dccg401_set_dpstreamclk( + dccg401_enable_dpstreamclk(dccg, otg_inst, dp_hpo_inst); + } + ++static void dccg401_enable_hdmistreamclk(struct dccg *dccg, int otg_inst, int hdmi_hpo_inst) ++{ ++ struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); ++ ++ /* enabled to select one of the DTBCLKs for pipe */ ++ switch (hdmi_hpo_inst) { ++ case 0: ++ if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream) { ++ REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, ++ HDMISTREAMCLK0_ROOT_GATE_DISABLE, 1); ++ REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, ++ HDMISTREAMCLK0_GATE_DISABLE, 1); ++ } ++ REG_UPDATE_2(HDMISTREAMCLK_CNTL, ++ HDMISTREAMCLK0_SRC_SEL, otg_inst, ++ HDMISTREAMCLK0_EN, 1); ++ break; ++ default: ++ BREAK_TO_DEBUGGER(); ++ return; ++ } ++} ++ ++static void dccg401_disable_hdmistreamclk(struct dccg *dccg, int hdmi_hpo_inst) ++{ ++ struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); ++ ++ switch (hdmi_hpo_inst) { ++ case 0: ++ REG_UPDATE(HDMISTREAMCLK_CNTL, ++ HDMISTREAMCLK0_EN, 0); ++ if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream) { ++ REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, ++ HDMISTREAMCLK0_ROOT_GATE_DISABLE, 0); ++ REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, ++ HDMISTREAMCLK0_GATE_DISABLE, 0); ++ } ++ break; ++ default: ++ BREAK_TO_DEBUGGER(); ++ return; ++ } ++} ++ ++void dccg401_set_hdmistreamclk( ++ struct dccg *dccg, ++ enum streamclk_source src, ++ int otg_inst, ++ int hdmi_hpo_inst) ++{ ++ /* enabled to select one of the DTBCLKs for pipe */ ++ if (src == REFCLK) ++ dccg401_disable_hdmistreamclk(dccg, hdmi_hpo_inst); ++ else ++ dccg401_enable_hdmistreamclk(dccg, otg_inst, hdmi_hpo_inst); ++} ++ + void dccg401_set_dp_dto( + struct dccg *dccg, + const struct dp_dto_params *params) +@@ -867,6 +924,7 @@ static const struct dccg_funcs dccg401_funcs = { + .get_dccg_ref_freq = dccg401_get_dccg_ref_freq, + .dccg_init = dccg401_init, + .set_dpstreamclk = dccg401_set_dpstreamclk, ++ .set_hdmistreamclk = dccg401_set_hdmistreamclk, + .enable_symclk32_se = dccg31_enable_symclk32_se, + .disable_symclk32_se = dccg31_disable_symclk32_se, + .enable_symclk32_le = dccg401_enable_symclk32_le, +diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h +index 5947a35363aa..47c755351a30 100644 +--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h ++++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h +@@ -201,6 +201,11 @@ void dccg401_set_dpstreamclk( + enum streamclk_source src, + int otg_inst, + int dp_hpo_inst); ++void dccg401_set_hdmistreamclk( ++ struct dccg *dccg, ++ enum streamclk_source src, ++ int otg_inst, ++ int hdmi_hpo_inst); + void dccg401_enable_symclk32_le( + struct dccg *dccg, + int hpo_le_inst, +diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c +index 13e14aad3daa..32d125d7f1d7 100644 +--- a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c +@@ -623,6 +623,10 @@ static bool dcn10_link_encoder_validate_hdmi_output( + enum dc_color_depth max_deep_color = + enc10->base.features.max_hdmi_deep_color; + ++ // FRL is always fine. TODO add validation ++ if (edid_caps->frl_caps.max_rate > 0) ++ return true; ++ + // check pixel clock against edid specified max TMDS clk + if (edid_caps->max_tmds_clk_mhz != 0 && + adjusted_pix_clk_100hz > edid_caps->max_tmds_clk_mhz * 10000) +@@ -804,6 +808,7 @@ bool dcn10_link_encoder_validate_output_with_stream( + &stream->timing); + break; + case SIGNAL_TYPE_HDMI_TYPE_A: ++ case SIGNAL_TYPE_HDMI_FRL: + is_valid = dcn10_link_encoder_validate_hdmi_output( + enc10, + &stream->timing, +diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c +index 07d362ef0daf..a721fef7d484 100644 +--- a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c +@@ -387,6 +387,7 @@ void dcn31_link_encoder_construct( + enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN; + enc10->base.features.flags.bits.DP_IS_USB_C = + bp_cap_info.DP_IS_USB_C; ++ enc10->base.features.flags.bits.IS_HDMI_FRL_CAPABLE = 1; + } else { + DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", + __func__, +diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c +index 65d28cb07b04..b55905cfeabd 100644 +--- a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c +@@ -329,6 +329,7 @@ void dcn32_link_encoder_construct( + enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN; + enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN; + enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN; ++ enc10->base.features.flags.bits.IS_HDMI_FRL_CAPABLE = 1; + } else { + DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", + __func__, +diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c +index 968f89295b64..8549359f55a8 100644 +--- a/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c +@@ -183,6 +183,7 @@ void dcn321_link_encoder_construct( + enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN; + enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN; + enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN; ++ enc10->base.features.flags.bits.IS_HDMI_FRL_CAPABLE = 1; + } else { + DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", + __func__, +diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c +index 20bf04dac609..6af1ca576d20 100644 +--- a/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c +@@ -260,6 +260,7 @@ void dcn35_link_encoder_construct( + enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN; + enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN; + enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN; ++ enc10->base.features.flags.bits.IS_HDMI_FRL_CAPABLE = 1; + + } else { + DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", +diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c +index e1f0a1bf1075..b3612f7a890d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c +@@ -314,6 +314,7 @@ void dcn401_link_encoder_construct( + enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN; + enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN; + enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN; ++ enc10->base.features.flags.bits.IS_HDMI_FRL_CAPABLE = 1; + } else { + DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", + __func__, +diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h +index 7014b8c2c956..5e77deb09200 100644 +--- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h ++++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h +@@ -220,10 +220,10 @@ int dm_helpers_dmub_set_config_sync(struct dc_context *ctx, + const struct dc_link *link, + struct set_config_cmd_payload *payload, + enum set_config_status *operation_result); +-enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link); + + enum dc_edid_status dm_helpers_get_sbios_edid(struct dc_link *link, struct dc_edid *edid); + ++bool dm_helpers_is_vrr_pcon_allowed(const struct dc_link *link, const struct drm_device *dev); + bool dm_helpers_is_fullscreen(struct dc_context *ctx, struct dc_stream_state *stream); + bool dm_helpers_is_hdr_on(struct dc_context *ctx, struct dc_stream_state *stream); + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +index 7aaf13bbd4e4..867e5a198155 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +@@ -1050,6 +1050,8 @@ static bool is_dtbclk_required(struct dc *dc, struct dc_state *context) + continue; + if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i])) + return true; ++ if (dc_is_hdmi_frl_signal(context->res_ctx.pipe_ctx[i].stream->signal)) ++ return true; + } + return false; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +index 8a0f128722b0..29cbc6db6cd2 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +@@ -1606,6 +1606,8 @@ static bool is_dtbclk_required(struct dc *dc, struct dc_state *context) + continue; + if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i])) + return true; ++ if (dc_is_hdmi_frl_signal(context->res_ctx.pipe_ctx[i].stream->signal)) ++ return true; + } + return false; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c +index bf5e7f4e0416..da55c52cd492 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c ++++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c +@@ -202,6 +202,9 @@ static void populate_dml21_output_config_from_stream_state(struct dml2_link_outp + case SIGNAL_TYPE_DVI_DUAL_LINK: + output->output_encoder = dml2_hdmi; + break; ++ case SIGNAL_TYPE_HDMI_FRL: ++ output->output_encoder = dml2_hdmifrl; ++ break; + default: + output->output_encoder = dml2_dp; + } +@@ -230,6 +233,7 @@ static void populate_dml21_output_config_from_stream_state(struct dml2_link_outp + case SIGNAL_TYPE_DVI_SINGLE_LINK: + case SIGNAL_TYPE_DVI_DUAL_LINK: + case SIGNAL_TYPE_HDMI_TYPE_A: ++ case SIGNAL_TYPE_HDMI_FRL: + case SIGNAL_TYPE_LVDS: + case SIGNAL_TYPE_RGB: + case SIGNAL_TYPE_DISPLAY_PORT: +diff --git a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c +index 73a1e6a03719..5aa1f15ee4cc 100644 +--- a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c ++++ b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c +@@ -345,6 +345,7 @@ static const struct protection_properties *get_protection_properties_by_signal( + case SIGNAL_TYPE_DVI_SINGLE_LINK: + case SIGNAL_TYPE_DVI_DUAL_LINK: + case SIGNAL_TYPE_HDMI_TYPE_A: ++ case SIGNAL_TYPE_HDMI_FRL: + return &hdmi_14_protection; + case SIGNAL_TYPE_DISPLAY_PORT: + if (link && +@@ -365,6 +366,7 @@ static const struct protection_properties *get_protection_properties_by_signal( + case SIGNAL_TYPE_DVI_SINGLE_LINK: + case SIGNAL_TYPE_DVI_DUAL_LINK: + case SIGNAL_TYPE_HDMI_TYPE_A: ++ case SIGNAL_TYPE_HDMI_FRL: + return &hdmi_14_protection; //todo version2.2 + case SIGNAL_TYPE_DISPLAY_PORT: + case SIGNAL_TYPE_DISPLAY_PORT_MST: +diff --git a/drivers/gpu/drm/amd/display/dc/hpo/Makefile b/drivers/gpu/drm/amd/display/dc/hpo/Makefile +index 7f2c9ee0dff1..53bb6ab5616a 100644 +--- a/drivers/gpu/drm/amd/display/dc/hpo/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/hpo/Makefile +@@ -27,6 +27,7 @@ ifdef CONFIG_DRM_AMD_DC_FP + ############################################################################### + # DCN30 + ############################################################################### ++HPO_DCN30 += dcn30_hpo_hdmi_stream_encoder.o dcn30_hpo_hdmi_link_encoder.o + + AMD_DAL_HPO_DCN30 = $(addprefix $(AMDDALPATH)/dc/hpo/dcn30/,$(HPO_DCN30)) + +diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_hdmi_link_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_hdmi_link_encoder.c +new file mode 100644 +index 000000000000..7373d8a135f8 +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_hdmi_link_encoder.c +@@ -0,0 +1,179 @@ ++/* ++ * HPO HDMI Link Encoder ++ * ++ * Copyright 2026 Michał Kopeć ++ */ ++ ++#include "dc_bios_types.h" ++#include "dcn30_hpo_hdmi_link_encoder.h" ++#include "reg_helper.h" ++#include "stream_encoder.h" ++#include "dc_bios_types.h" ++ ++#define DC_LOGGER enc3->base.ctx->logger ++ ++#define REG(reg) (enc3->regs->reg) ++ ++#undef FN ++#define FN(reg_name, field_name) \ ++ enc3->shift->field_name, enc3->mask->field_name ++ ++#define CTX enc3->base.ctx ++ ++static void dcn30_hpo_hdmi_link_enc_enable(struct hpo_hdmi_link_encoder *enc, ++ uint8_t lane_count) ++{ ++ struct dcn30_hpo_hdmi_link_encoder *enc3 = ++ DCN3_0_HPO_HDMI_LINK_ENC_FROM_HPO_LINK_ENC(enc); ++ ++ REG_UPDATE(HDMI_LINK_ENC_CLK_CTRL, HDMI_LINK_ENC_CLOCK_EN, 1); ++ ++ REG_UPDATE(HDMI_FRL_ENC_CONFIG, HDMI_LINK_LANE_COUNT, ++ (lane_count == 4) ? 1 : 0); ++ ++ REG_UPDATE(HDMI_LINK_ENC_CONTROL, HDMI_LINK_ENC_SOFT_RESET, 1); ++ REG_UPDATE(HDMI_LINK_ENC_CONTROL, HDMI_LINK_ENC_SOFT_RESET, 0); ++ ++ REG_UPDATE(HDMI_LINK_ENC_CONTROL, HDMI_LINK_ENC_ENABLE, 1); ++} ++ ++static void dcn30_hpo_hdmi_link_enc_disable(struct hpo_hdmi_link_encoder *enc) ++{ ++ struct dcn30_hpo_hdmi_link_encoder *enc3 = ++ DCN3_0_HPO_HDMI_LINK_ENC_FROM_HPO_LINK_ENC(enc); ++ ++ REG_UPDATE_4(HDMI_FRL_ENC_CONFIG, HDMI_LINK_LANE0_TRAINING_PATTERN, 0, ++ HDMI_LINK_LANE1_TRAINING_PATTERN, 0, ++ HDMI_LINK_LANE2_TRAINING_PATTERN, 0, ++ HDMI_LINK_LANE3_TRAINING_PATTERN, 0); ++ ++ // If this is disabled here and the link is later re-enabled, the ++ // meterbuffer will overflow, requiring a full platform reset to reset. ++ // For some reason enabling training mode fixes that issue. ++ REG_UPDATE(HDMI_FRL_ENC_CONFIG, HDMI_LINK_TRAINING_ENABLE, 1); ++ ++ REG_UPDATE(HDMI_LINK_ENC_CONTROL, HDMI_LINK_ENC_ENABLE, 0); ++ ++ REG_UPDATE(HDMI_LINK_ENC_CLK_CTRL, HDMI_LINK_ENC_CLOCK_EN, 0); ++} ++ ++static enum bp_result ++link_transmitter_control(struct dcn30_hpo_hdmi_link_encoder *enc3, ++ struct bp_transmitter_control *cntl) ++{ ++ enum bp_result result; ++ struct dc_bios *bp = enc3->base.ctx->dc_bios; ++ ++ result = bp->funcs->transmitter_control(bp, cntl); ++ ++ return result; ++} ++ ++static uint32_t hdmi_frl_rate_to_pixel_clock(uint8_t frl_rate) ++{ ++ /* Lane rate in Gbps per HDMI 2.1 spec */ ++ static const uint8_t frl_lane_rate_gbps[] = { ++ [1] = 3, [2] = 6, [3] = 6, [4] = 8, [5] = 10, [6] = 12, ++ }; ++ ++ uint32_t lane_rate_gbps; ++ ++ if (frl_rate < 1 || frl_rate > 6) ++ return 0; ++ ++ lane_rate_gbps = frl_lane_rate_gbps[frl_rate]; ++ ++ /* ++ * HDMI 2.1 FRL uses 16b/18b encoding. ++ * Character clock = lane_rate / 18. ++ */ ++ return (lane_rate_gbps * 1000000) / 18; ++} ++ ++static void dcn30_hpo_hdmi_link_enc_configure_transmitter( ++ struct hpo_hdmi_link_encoder *enc, const struct dc_link *link, ++ uint8_t frl_rate, enum transmitter transmitter, ++ enum hpd_source_id hpd_source) ++{ ++ struct dcn30_hpo_hdmi_link_encoder *enc3 = ++ DCN3_0_HPO_HDMI_LINK_ENC_FROM_HPO_LINK_ENC(enc); ++ struct bp_transmitter_control cntl = { 0 }; ++ enum bp_result result; ++ ++ /* Set the transmitter */ ++ enc3->base.transmitter = transmitter; ++ ++ /* Set the hpd source */ ++ enc3->base.hpd_source = hpd_source; ++ ++ cntl.action = TRANSMITTER_CONTROL_ENABLE; ++ cntl.engine_id = enc3->base.preferred_engine; ++ cntl.transmitter = enc3->base.transmitter; ++ cntl.signal = SIGNAL_TYPE_HDMI_FRL; ++ cntl.lanes_number = (frl_rate <= 2) ? 3 : 4; ++ cntl.hpd_sel = enc3->base.hpd_source; ++ cntl.pixel_clock = hdmi_frl_rate_to_pixel_clock(frl_rate); ++ cntl.color_depth = COLOR_DEPTH_UNDEFINED; ++ cntl.hpo_engine_id = enc->inst + ENGINE_ID_HPO_0; ++ ++ result = link_transmitter_control(enc3, &cntl); ++ ++ if (result != BP_RESULT_OK) { ++ DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", ++ __func__); ++ BREAK_TO_DEBUGGER(); ++ return; ++ } ++} ++ ++static void dcn30_hpo_hdmi_link_enc_set_training_enable( ++ struct hpo_hdmi_link_encoder *enc, bool enable) ++{ ++ struct dcn30_hpo_hdmi_link_encoder *enc3 = ++ DCN3_0_HPO_HDMI_LINK_ENC_FROM_HPO_LINK_ENC(enc); ++ ++ REG_UPDATE(HDMI_FRL_ENC_CONFIG, HDMI_LINK_TRAINING_ENABLE, enable); ++} ++ ++static void dcn30_hpo_hdmi_link_enc_set_training_patterns( ++ struct hpo_hdmi_link_encoder *enc, uint8_t lane0_ltp, uint8_t lane1_ltp, ++ uint8_t lane2_ltp, uint8_t lane3_ltp) ++{ ++ struct dcn30_hpo_hdmi_link_encoder *enc3 = ++ DCN3_0_HPO_HDMI_LINK_ENC_FROM_HPO_LINK_ENC(enc); ++ ++ REG_UPDATE_4(HDMI_FRL_ENC_CONFIG, HDMI_LINK_LANE0_TRAINING_PATTERN, ++ lane0_ltp, HDMI_LINK_LANE1_TRAINING_PATTERN, lane1_ltp, ++ HDMI_LINK_LANE2_TRAINING_PATTERN, lane2_ltp, ++ HDMI_LINK_LANE3_TRAINING_PATTERN, lane3_ltp); ++} ++ ++static const struct hpo_hdmi_link_encoder_funcs ++ dcn30_hpo_hdmi_link_encoder_funcs = { ++ .link_enable = dcn30_hpo_hdmi_link_enc_enable, ++ .link_disable = dcn30_hpo_hdmi_link_enc_disable, ++ .configure_transmitter = ++ dcn30_hpo_hdmi_link_enc_configure_transmitter, ++ .set_training_enable = ++ dcn30_hpo_hdmi_link_enc_set_training_enable, ++ .set_training_patterns = ++ dcn30_hpo_hdmi_link_enc_set_training_patterns, ++ }; ++ ++void hpo_hdmi_link_encoder31_construct( ++ struct dcn30_hpo_hdmi_link_encoder *enc3, struct dc_context *ctx, ++ uint32_t inst, const struct dcn30_hpo_hdmi_link_encoder_registers *regs, ++ const struct dcn30_hpo_hdmi_link_encoder_shift *shift, ++ const struct dcn30_hpo_hdmi_link_encoder_mask *mask) ++{ ++ enc3->base.ctx = ctx; ++ ++ enc3->base.inst = inst; ++ enc3->base.funcs = &dcn30_hpo_hdmi_link_encoder_funcs; ++ enc3->base.hpd_source = HPD_SOURCEID_UNKNOWN; ++ enc3->base.transmitter = TRANSMITTER_UNKNOWN; ++ ++ enc3->regs = regs; ++ enc3->shift = shift; ++ enc3->mask = mask; ++} +diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_hdmi_link_encoder.h b/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_hdmi_link_encoder.h +new file mode 100644 +index 000000000000..134d2ca1dc17 +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_hdmi_link_encoder.h +@@ -0,0 +1,131 @@ ++/* ++ * HPO HDMI Link Encoder ++ * ++ * Copyright 2026 Michał Kopeć ++ */ ++ ++#ifndef __DAL_DCN401_HPO_HDMI_LINK_ENCODER_H__ ++#define __DAL_DCN401_HPO_HDMI_LINK_ENCODER_H__ ++ ++#include "link_encoder.h" ++ ++#define DCN3_0_HPO_HDMI_LINK_ENC_FROM_HPO_LINK_ENC(hpo_hdmi_link_encoder) \ ++ container_of(hpo_hdmi_link_encoder, \ ++ struct dcn30_hpo_hdmi_link_encoder, base) ++ ++#define DCN3_0_HPO_HDMI_LINK_ENC_REG_LIST() \ ++ SR(HDMI_LINK_ENC_CONTROL), SR(HDMI_LINK_ENC_CLK_CTRL), \ ++ SR(HDMI_FRL_ENC_CONFIG), SR(HDMI_FRL_ENC_CONFIG2), \ ++ SR(HDMI_FRL_ENC_METER_BUFFER_STATUS), \ ++ SR(HDMI_FRL_ENC_MEM_CTRL) ++ ++#define DCN3_0_HPO_HDMI_LINK_ENC_REGS \ ++ uint32_t HDMI_LINK_ENC_CONTROL; \ ++ uint32_t HDMI_LINK_ENC_CLK_CTRL; \ ++ uint32_t HDMI_FRL_ENC_CONFIG; \ ++ uint32_t HDMI_FRL_ENC_CONFIG2; \ ++ uint32_t HDMI_FRL_ENC_METER_BUFFER_STATUS; \ ++ uint32_t HDMI_FRL_ENC_MEM_CTRL; ++ ++struct dcn30_hpo_hdmi_link_encoder_registers { ++ DCN3_0_HPO_HDMI_LINK_ENC_REGS; ++}; ++ ++#define DCN3_0_HPO_HDMI_LINK_ENC_MASK_SH_LIST(mask_sh) \ ++ SE_SF(HDMI_LINK_ENC_CONTROL, HDMI_LINK_ENC_ENABLE, mask_sh), \ ++ SE_SF(HDMI_LINK_ENC_CONTROL, HDMI_LINK_ENC_SOFT_RESET, mask_sh), \ ++ SE_SF(HDMI_LINK_ENC_CLK_CTRL, HDMI_LINK_ENC_CLOCK_EN, \ ++ mask_sh), \ ++ SE_SF(HDMI_LINK_ENC_CLK_CTRL, \ ++ HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK, mask_sh), \ ++ SE_SF(HDMI_FRL_ENC_CONFIG, HDMI_LINK_LANE_COUNT, mask_sh), \ ++ SE_SF(HDMI_FRL_ENC_CONFIG, HDMI_LINK_TRAINING_ENABLE, \ ++ mask_sh), \ ++ SE_SF(HDMI_FRL_ENC_CONFIG, HDMI_LINK_SCRAMBLER_DISABLE, \ ++ mask_sh), \ ++ SE_SF(HDMI_FRL_ENC_CONFIG, HDMI_LINK_LANE0_TRAINING_PATTERN, \ ++ mask_sh), \ ++ SE_SF(HDMI_FRL_ENC_CONFIG, HDMI_LINK_LANE1_TRAINING_PATTERN, \ ++ mask_sh), \ ++ SE_SF(HDMI_FRL_ENC_CONFIG, HDMI_LINK_LANE2_TRAINING_PATTERN, \ ++ mask_sh), \ ++ SE_SF(HDMI_FRL_ENC_CONFIG, HDMI_LINK_LANE3_TRAINING_PATTERN, \ ++ mask_sh), \ ++ SE_SF(HDMI_FRL_ENC_CONFIG2, HDMI_LINK_MAX_JITTER_VALUE, \ ++ mask_sh), \ ++ SE_SF(HDMI_FRL_ENC_CONFIG2, HDMI_LINK_JITTER_THRESHOLD, \ ++ mask_sh), \ ++ SE_SF(HDMI_FRL_ENC_CONFIG2, HDMI_LINK_JITTER_CAL_EN, mask_sh), \ ++ SE_SF(HDMI_FRL_ENC_CONFIG2, HDMI_LINK_RC_COMPRESS_DISABLE, \ ++ mask_sh), \ ++ SE_SF(HDMI_FRL_ENC_CONFIG2, HDMI_FRL_HDMISTREAMCLK_DB_SEL, \ ++ mask_sh), \ ++ SE_SF(HDMI_FRL_ENC_CONFIG2, HDMI_LINK_MAX_JITTER_VALUE_RESET, \ ++ mask_sh), \ ++ SE_SF(HDMI_FRL_ENC_CONFIG2, HDMI_LINK_JITTER_EXCEED_STATUS, \ ++ mask_sh), \ ++ SE_SF(HDMI_FRL_ENC_CONFIG2, \ ++ HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS, mask_sh), \ ++ SE_SF(HDMI_FRL_ENC_METER_BUFFER_STATUS, \ ++ HDMI_LINK_MAX_METER_BUFFER_LEVEL, mask_sh), \ ++ SE_SF(HDMI_FRL_ENC_METER_BUFFER_STATUS, \ ++ HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET, mask_sh), \ ++ SE_SF(HDMI_FRL_ENC_MEM_CTRL, METERBUFFER_MEM_PWR_DIS, \ ++ mask_sh), \ ++ SE_SF(HDMI_FRL_ENC_MEM_CTRL, METERBUFFER_MEM_PWR_FORCE, \ ++ mask_sh), \ ++ SE_SF(HDMI_FRL_ENC_MEM_CTRL, METERBUFFER_MEM_PWR_STATE, \ ++ mask_sh), \ ++ SE_SF(HDMI_FRL_ENC_MEM_CTRL, \ ++ METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE, mask_sh) ++ ++#define DCN3_0_HPO_HDMI_LINK_ENC_REG_FIELD_LIST(type) \ ++ type HDMI_LINK_ENC_ENABLE; \ ++ type HDMI_LINK_ENC_SOFT_RESET; \ ++ type HDMI_LINK_ENC_CLOCK_EN; \ ++ type HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK; \ ++ type HDMI_LINK_LANE_COUNT; \ ++ type HDMI_LINK_TRAINING_ENABLE; \ ++ type HDMI_LINK_SCRAMBLER_DISABLE; \ ++ type HDMI_LINK_LANE0_TRAINING_PATTERN; \ ++ type HDMI_LINK_LANE1_TRAINING_PATTERN; \ ++ type HDMI_LINK_LANE2_TRAINING_PATTERN; \ ++ type HDMI_LINK_LANE3_TRAINING_PATTERN; \ ++ type HDMI_LINK_MAX_JITTER_VALUE; \ ++ type HDMI_LINK_JITTER_THRESHOLD; \ ++ type HDMI_LINK_JITTER_CAL_EN; \ ++ type HDMI_LINK_RC_COMPRESS_DISABLE; \ ++ type HDMI_FRL_HDMISTREAMCLK_DB_SEL; \ ++ type HDMI_LINK_MAX_JITTER_VALUE_RESET; \ ++ type HDMI_LINK_JITTER_EXCEED_STATUS; \ ++ type HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS; \ ++ type HDMI_LINK_MAX_METER_BUFFER_LEVEL; \ ++ type HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET; \ ++ type METERBUFFER_MEM_PWR_DIS; \ ++ type METERBUFFER_MEM_PWR_FORCE; \ ++ type METERBUFFER_MEM_PWR_STATE; \ ++ type METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE ++ ++struct dcn30_hpo_hdmi_link_encoder_shift { ++ DCN3_0_HPO_HDMI_LINK_ENC_REG_FIELD_LIST(uint8_t); ++}; ++ ++struct dcn30_hpo_hdmi_link_encoder_mask { ++ DCN3_0_HPO_HDMI_LINK_ENC_REG_FIELD_LIST(uint32_t); ++}; ++ ++struct dcn30_hpo_hdmi_link_encoder { ++ struct hpo_hdmi_link_encoder base; ++ ++ const struct dcn30_hpo_hdmi_link_encoder_registers *regs; ++ const struct dcn30_hpo_hdmi_link_encoder_shift *shift; ++ const struct dcn30_hpo_hdmi_link_encoder_mask *mask; ++}; ++ ++void hpo_hdmi_link_encoder31_construct( ++ struct dcn30_hpo_hdmi_link_encoder *enc3, struct dc_context *ctx, ++ uint32_t inst, const struct dcn30_hpo_hdmi_link_encoder_registers *regs, ++ const struct dcn30_hpo_hdmi_link_encoder_shift *shift, ++ const struct dcn30_hpo_hdmi_link_encoder_mask *mask); ++ ++#endif /* __DAL_DCN401_HPO_HDMI_LINK_ENCODER_H__ */ +diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_hdmi_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_hdmi_stream_encoder.c +new file mode 100644 +index 000000000000..3cc437683b2c +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_hdmi_stream_encoder.c +@@ -0,0 +1,523 @@ ++/* ++ * HPO HDMI Stream Encoder ++ * ++ * Copyright 2026 Michał Kopeć ++ */ ++ ++#include "dc_bios_types.h" ++#include "dcn30_hpo_hdmi_stream_encoder.h" ++#include "reg_helper.h" ++#include "dc.h" ++ ++#define DC_LOGGER enc3->base.ctx->logger ++ ++#define REG(reg) (enc3->regs->reg) ++ ++#undef FN ++#define FN(reg_name, field_name) \ ++ enc3->hpo_se_shift->field_name, enc3->hpo_se_mask->field_name ++ ++#define VBI_LINE_0 0 ++ ++#define CTX enc3->base.ctx ++ ++static void ++dcn30_hpo_hdmi_stream_enc_enable(struct hpo_hdmi_stream_encoder *enc, ++ uint8_t source_select) ++{ ++ struct dcn30_hpo_hdmi_stream_encoder *enc3 = ++ DCN3_0_HPO_HDMI_STREAM_ENC_FROM_HPO_STREAM_ENC(enc); ++ ++ /* ++ * Enable all clock domains first - clocks must be running ++ * before we attempt any reset or FIFO operation. ++ */ ++ REG_UPDATE_4(HDMI_STREAM_ENC_CLOCK_CONTROL, HDMI_STREAM_ENC_CLOCK_EN, 1, ++ HDMI_STREAM_ENC_CLOCK_ON_DISPCLK, 1, ++ HDMI_STREAM_ENC_CLOCK_ON_SOCCLK, 1, ++ HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK, 1); ++ ++ REG_UPDATE(HDMI_STREAM_ENC_INPUT_MUX_CONTROL, ++ HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL, source_select); ++ ++ REG_UPDATE(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, ++ FIFO_RESET, 1); ++ ++ REG_WAIT(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, ++ FIFO_RESET_DONE, 1, 10, 1000); ++ ++ REG_UPDATE(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, ++ FIFO_RESET, 0); ++ ++ REG_WAIT(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, ++ FIFO_RESET_DONE, 0, 10, 1000); ++ ++ REG_UPDATE(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, ++ FIFO_ENABLE, 1); ++ ++ REG_UPDATE(HDMI_TB_ENC_CONTROL, HDMI_RESET, 1); ++ ++ REG_WAIT(HDMI_TB_ENC_CONTROL, HDMI_RESET_DONE, 1, 10, 1000); ++ ++ REG_UPDATE(HDMI_TB_ENC_CONTROL, HDMI_RESET, 0); ++ ++ REG_WAIT(HDMI_TB_ENC_CONTROL, HDMI_RESET_DONE, 0, 10, 1000); ++ ++ REG_UPDATE(HDMI_TB_ENC_CONTROL, HDMI_TB_ENC_EN, 1); ++} ++ ++static void ++dcn30_hpo_hdmi_stream_enc_disable(struct hpo_hdmi_stream_encoder *enc) ++{ ++ struct dcn30_hpo_hdmi_stream_encoder *enc3 = ++ DCN3_0_HPO_HDMI_STREAM_ENC_FROM_HPO_STREAM_ENC(enc); ++ ++ /* Disable TB encoder first */ ++ REG_UPDATE(HDMI_TB_ENC_CONTROL, HDMI_TB_ENC_EN, 0); ++ ++ /* Disable FIFO */ ++ REG_UPDATE(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, ++ FIFO_ENABLE, 0); ++ ++ /* Disable all clock domains */ ++ REG_UPDATE_4(HDMI_STREAM_ENC_CLOCK_CONTROL, HDMI_STREAM_ENC_CLOCK_EN, 0, ++ HDMI_STREAM_ENC_CLOCK_ON_DISPCLK, 0, ++ HDMI_STREAM_ENC_CLOCK_ON_SOCCLK, 0, ++ HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK, 0); ++} ++ ++static void dcn30_hpo_hdmi_stream_enc_update_info_packet( ++ struct dcn30_hpo_hdmi_stream_encoder *enc3, uint32_t packet_index, ++ const struct dc_info_packet *info_packet) ++{ ++ uint32_t cont, send, line; ++ ++ if (info_packet->valid) { ++ /* ++ * Write packet data via VPG - same as DIO path. ++ * VPG is shared infrastructure, works identically ++ * for both DIO and HPO encoders. ++ */ ++ enc3->base.vpg->funcs->update_generic_info_packet( ++ enc3->base.vpg, packet_index, info_packet, true); ++ ++ cont = 1; ++ send = 1; ++ line = 2; ++ } else { ++ cont = 0; ++ send = 0; ++ line = 0; ++ } ++ ++ /* ++ * Enable/disable packet transmission via TB encoder registers. ++ * Layout mirrors DIO enc3_update_hdmi_info_packet() but uses ++ * HDMI_TB_ENC_GENERIC_PACKET_CONTROL* registers. ++ * ++ * CONTROL0/1 handle SEND+CONT for all 15 packets. ++ * LINE registers pack two packets each. ++ */ ++ switch (packet_index) { ++ case 0: ++ REG_UPDATE_2(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, ++ HDMI_GENERIC0_SEND, send, HDMI_GENERIC0_CONT, ++ cont); ++ REG_UPDATE(HDMI_TB_ENC_GENERIC_PACKET0_1_LINE, ++ HDMI_GENERIC0_LINE, line); ++ break; ++ case 1: ++ REG_UPDATE_2(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, ++ HDMI_GENERIC1_SEND, send, HDMI_GENERIC1_CONT, ++ cont); ++ REG_UPDATE(HDMI_TB_ENC_GENERIC_PACKET0_1_LINE, ++ HDMI_GENERIC1_LINE, line); ++ break; ++ case 2: ++ REG_UPDATE_2(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, ++ HDMI_GENERIC2_SEND, send, HDMI_GENERIC2_CONT, ++ cont); ++ REG_UPDATE(HDMI_TB_ENC_GENERIC_PACKET2_3_LINE, ++ HDMI_GENERIC2_LINE, line); ++ break; ++ case 3: ++ REG_UPDATE_2(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, ++ HDMI_GENERIC3_SEND, send, HDMI_GENERIC3_CONT, ++ cont); ++ REG_UPDATE(HDMI_TB_ENC_GENERIC_PACKET2_3_LINE, ++ HDMI_GENERIC3_LINE, line); ++ break; ++ case 4: ++ REG_UPDATE_2(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, ++ HDMI_GENERIC4_SEND, send, HDMI_GENERIC4_CONT, ++ cont); ++ REG_UPDATE(HDMI_TB_ENC_GENERIC_PACKET4_5_LINE, ++ HDMI_GENERIC4_LINE, line); ++ break; ++ case 5: ++ REG_UPDATE_2(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, ++ HDMI_GENERIC5_SEND, send, HDMI_GENERIC5_CONT, ++ cont); ++ REG_UPDATE(HDMI_TB_ENC_GENERIC_PACKET4_5_LINE, ++ HDMI_GENERIC5_LINE, line); ++ break; ++ case 6: ++ REG_UPDATE_2(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, ++ HDMI_GENERIC6_SEND, send, HDMI_GENERIC6_CONT, ++ cont); ++ REG_UPDATE(HDMI_TB_ENC_GENERIC_PACKET6_7_LINE, ++ HDMI_GENERIC6_LINE, line); ++ break; ++ case 7: ++ REG_UPDATE_2(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, ++ HDMI_GENERIC7_SEND, send, HDMI_GENERIC7_CONT, ++ cont); ++ REG_UPDATE(HDMI_TB_ENC_GENERIC_PACKET6_7_LINE, ++ HDMI_GENERIC7_LINE, line); ++ break; ++ case 8: ++ REG_UPDATE_2(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, ++ HDMI_GENERIC8_SEND, send, HDMI_GENERIC8_CONT, ++ cont); ++ REG_UPDATE(HDMI_TB_ENC_GENERIC_PACKET8_9_LINE, ++ HDMI_GENERIC8_LINE, line); ++ break; ++ case 9: ++ REG_UPDATE_2(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, ++ HDMI_GENERIC9_SEND, send, HDMI_GENERIC9_CONT, ++ cont); ++ REG_UPDATE(HDMI_TB_ENC_GENERIC_PACKET8_9_LINE, ++ HDMI_GENERIC9_LINE, line); ++ break; ++ case 10: ++ REG_UPDATE_2(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, ++ HDMI_GENERIC10_SEND, send, HDMI_GENERIC10_CONT, ++ cont); ++ REG_UPDATE(HDMI_TB_ENC_GENERIC_PACKET10_11_LINE, ++ HDMI_GENERIC10_LINE, line); ++ break; ++ case 11: ++ REG_UPDATE_2(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, ++ HDMI_GENERIC11_SEND, send, HDMI_GENERIC11_CONT, ++ cont); ++ REG_UPDATE(HDMI_TB_ENC_GENERIC_PACKET10_11_LINE, ++ HDMI_GENERIC11_LINE, line); ++ break; ++ case 12: ++ REG_UPDATE_2(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, ++ HDMI_GENERIC12_SEND, send, HDMI_GENERIC12_CONT, ++ cont); ++ REG_UPDATE(HDMI_TB_ENC_GENERIC_PACKET12_13_LINE, ++ HDMI_GENERIC12_LINE, line); ++ break; ++ case 13: ++ REG_UPDATE_2(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, ++ HDMI_GENERIC13_SEND, send, HDMI_GENERIC13_CONT, ++ cont); ++ REG_UPDATE(HDMI_TB_ENC_GENERIC_PACKET12_13_LINE, ++ HDMI_GENERIC13_LINE, line); ++ break; ++ case 14: ++ REG_UPDATE_2(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, ++ HDMI_GENERIC14_SEND, send, HDMI_GENERIC14_CONT, ++ cont); ++ REG_UPDATE(HDMI_TB_ENC_GENERIC_PACKET14_LINE, ++ HDMI_GENERIC14_LINE, line); ++ break; ++ default: ++ DC_LOG_WARNING("Invalid packet index: %s()\n", __func__); ++ return; ++ } ++} ++ ++static void dcn30_hpo_hdmi_stream_enc_update_info_packets( ++ struct hpo_hdmi_stream_encoder *enc, ++ const struct encoder_info_frame *info_frame) ++{ ++ struct dcn30_hpo_hdmi_stream_encoder *enc3 = ++ DCN3_0_HPO_HDMI_STREAM_ENC_FROM_HPO_STREAM_ENC(enc); ++ ++ dcn30_hpo_hdmi_stream_enc_update_info_packet(enc3, 0, &info_frame->avi); ++ dcn30_hpo_hdmi_stream_enc_update_info_packet(enc3, 5, ++ &info_frame->hfvsif); ++ dcn30_hpo_hdmi_stream_enc_update_info_packet(enc3, 2, ++ &info_frame->gamut); ++ dcn30_hpo_hdmi_stream_enc_update_info_packet(enc3, 1, ++ &info_frame->vendor); ++ dcn30_hpo_hdmi_stream_enc_update_info_packet(enc3, 3, &info_frame->spd); ++ dcn30_hpo_hdmi_stream_enc_update_info_packet(enc3, 4, ++ &info_frame->hdrsmd); ++ dcn30_hpo_hdmi_stream_enc_update_info_packet(enc3, 6, ++ &info_frame->vtem); ++} ++ ++static void ++dcn30_hpo_hdmi_stream_enc_stop_info_packets(struct hpo_hdmi_stream_encoder *enc) ++{ ++ struct dcn30_hpo_hdmi_stream_encoder *enc3 = ++ DCN3_0_HPO_HDMI_STREAM_ENC_FROM_HPO_STREAM_ENC(enc); ++ ++ /* Disable all generic packet slots */ ++ REG_UPDATE_8(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, 0, ++ HDMI_GENERIC0_CONT, 0, HDMI_GENERIC1_SEND, 0, ++ HDMI_GENERIC1_CONT, 0, HDMI_GENERIC2_SEND, 0, ++ HDMI_GENERIC2_CONT, 0, HDMI_GENERIC3_SEND, 0, ++ HDMI_GENERIC3_CONT, 0); ++ ++ REG_UPDATE_8(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_SEND, 0, ++ HDMI_GENERIC4_CONT, 0, HDMI_GENERIC5_SEND, 0, ++ HDMI_GENERIC5_CONT, 0, HDMI_GENERIC6_SEND, 0, ++ HDMI_GENERIC6_CONT, 0, HDMI_GENERIC7_SEND, 0, ++ HDMI_GENERIC7_CONT, 0); ++ ++ REG_UPDATE_8(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, HDMI_GENERIC8_SEND, 0, ++ HDMI_GENERIC8_CONT, 0, HDMI_GENERIC9_SEND, 0, ++ HDMI_GENERIC9_CONT, 0, HDMI_GENERIC10_SEND, 0, ++ HDMI_GENERIC10_CONT, 0, HDMI_GENERIC11_SEND, 0, ++ HDMI_GENERIC11_CONT, 0); ++ ++ REG_UPDATE_6(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, HDMI_GENERIC12_SEND, ++ 0, HDMI_GENERIC12_CONT, 0, HDMI_GENERIC13_SEND, 0, ++ HDMI_GENERIC13_CONT, 0, HDMI_GENERIC14_SEND, 0, ++ HDMI_GENERIC14_CONT, 0); ++} ++ ++static void dcn30_hpo_hdmi_stream_enc_setup_stream_attribute( ++ struct hpo_hdmi_stream_encoder *enc, struct dc_crtc_timing *timing, ++ enum dc_color_space output_color_space) ++{ ++ struct dcn30_hpo_hdmi_stream_encoder *enc3 = ++ DCN3_0_HPO_HDMI_STREAM_ENC_FROM_HPO_STREAM_ENC(enc); ++ uint32_t h_blank; ++ ++ uint32_t pixel_encoding; ++ uint32_t deep_color_depth; ++ uint32_t deep_color_enable; ++ ++ switch (timing->pixel_encoding) { ++ case PIXEL_ENCODING_YCBCR422: ++ pixel_encoding = 1; ++ break; ++ case PIXEL_ENCODING_YCBCR420: ++ pixel_encoding = 2; ++ break; ++ case PIXEL_ENCODING_YCBCR444: ++ default: /* RGB */ ++ pixel_encoding = 0; ++ break; ++ } ++ ++ switch (timing->display_color_depth) { ++ case COLOR_DEPTH_888: ++ deep_color_depth = 0; ++ deep_color_enable = 0; ++ break; ++ case COLOR_DEPTH_101010: ++ deep_color_depth = 1; ++ deep_color_enable = ++ (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) ? ++ 1 : ++ 0; ++ break; ++ case COLOR_DEPTH_121212: ++ deep_color_depth = 2; ++ deep_color_enable = ++ (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) ? ++ 1 : ++ 0; ++ break; ++ case COLOR_DEPTH_161616: ++ deep_color_depth = 3; ++ deep_color_enable = 1; ++ break; ++ default: ++ deep_color_depth = 0; ++ deep_color_enable = 0; ++ break; ++ } ++ ++ REG_UPDATE_4(HDMI_TB_ENC_PIXEL_FORMAT, ++ HDMI_PIXEL_ENCODING, pixel_encoding, ++ HDMI_DEEP_COLOR_DEPTH, deep_color_depth, ++ HDMI_DEEP_COLOR_ENABLE, deep_color_enable, ++ HDMI_DSC_MODE, 0); ++ ++ /* H timing */ ++ h_blank = timing->h_total - timing->h_addressable - ++ timing->h_border_left - timing->h_border_right; ++ ++ REG_UPDATE_2(HDMI_TB_ENC_H_ACTIVE_BLANK, ++ HDMI_H_ACTIVE, timing->h_addressable, ++ HDMI_H_BLANK, h_blank); ++ ++ /* CRC */ ++ REG_UPDATE_2(HDMI_TB_ENC_CRC_CNTL, HDMI_CRC_EN, 1, HDMI_CRC_CONT_EN, 1); ++ ++ /* Borrow mode */ ++ REG_UPDATE(HDMI_TB_ENC_MODE, HDMI_BORROW_MODE, 1); ++ ++ /* Disable double buffering */ ++ REG_UPDATE(HDMI_TB_ENC_DB_CONTROL, HDMI_DB_DISABLE, 1); ++ ++ /* Max 1 packet per line */ ++ REG_UPDATE(HDMI_TB_ENC_PACKET_CONTROL, HDMI_MAX_PACKETS_PER_LINE, 1); ++ ++ /* Enable VBI packet transmission */ ++ REG_UPDATE_2(HDMI_TB_ENC_VBI_PACKET_CONTROL1, HDMI_GC_SEND, 1, ++ HDMI_GC_CONT, 1); ++ ++ /* Disable Audio Content Protection packet transmission */ ++ REG_UPDATE(HDMI_TB_ENC_VBI_PACKET_CONTROL1, HDMI_ACP_SEND, 0); ++ /* following belongs to audio */ ++ /* Enable Audio InfoFrame packet transmission. */ ++ REG_UPDATE(HDMI_TB_ENC_VBI_PACKET_CONTROL1, HDMI_AUDIO_INFO_SEND, 1); ++ ++ /* update double-buffered AUDIO_INFO registers immediately */ ++ ASSERT(enc->afmt); ++ enc->afmt->funcs->audio_info_immediate_update(enc->afmt); ++ ++ /* Select line number on which to send Audio InfoFrame packets */ ++ REG_UPDATE(HDMI_TB_ENC_VBI_PACKET_CONTROL1, HDMI_AUDIO_INFO_LINE, ++ VBI_LINE_0 + 2); ++ ++ /* Clear AVMUTE */ ++ REG_UPDATE(HDMI_TB_ENC_GC_CONTROL, HDMI_GC_AVMUTE, 0); ++} ++ ++struct frl_audio_clock_info { ++ uint32_t frl_lane_rate; ++ /* N - 32KHz audio */ ++ uint32_t n_32khz; ++ /* CTS - 32KHz audio*/ ++ uint32_t cts_32khz; ++ uint32_t n_44khz; ++ uint32_t cts_44khz; ++ uint32_t n_48khz; ++ uint32_t cts_48khz; ++}; ++ ++/* Values set by the Windows driver seem to depend only on FRL rate*/ ++static const struct frl_audio_clock_info frl_audio_clock_info_table[5] = { ++ {3, 4224, 171875, 5292, 156250, 5760, 156250}, ++ {6, 4032, 328125, 5292, 312500, 6048, 328125}, ++ {8, 4032, 437500, 3969, 312500, 6048, 437500}, ++ {10, 3456, 468750, 3969, 390625, 5184, 468750}, ++ {12, 3072, 500000, 3969, 468750, 4752, 515625}, ++}; ++ ++static void get_frl_audio_clock_info( ++ struct frl_audio_clock_info *audio_clock_info, ++ uint8_t frl_rate) ++{ ++ uint32_t index; ++ uint32_t frl_lane_rates[] = { 3, 6, 6, 8, 10, 12 }; ++ uint32_t frl_lane_rate; ++ ++ ASSERT(frl_rate >= 0 && frl_rate <= 6); ++ ++ frl_lane_rate = frl_lane_rates[frl_rate - 1]; ++ ++ /* search for FRL rate in table */ ++ for (index = 0; ++ index < sizeof(frl_audio_clock_info_table) / sizeof(struct frl_audio_clock_info); ++ index++) { ++ if (frl_audio_clock_info_table[index].frl_lane_rate == frl_lane_rate) { ++ *audio_clock_info = frl_audio_clock_info_table[index]; ++ return; ++ } ++ } ++ ++ /* Should never happen */ ++ *audio_clock_info = frl_audio_clock_info_table[0]; ++} ++ ++static void setup_hdmi_audio(struct hpo_hdmi_stream_encoder *enc, ++ const struct audio_crtc_info *crtc_info, uint8_t frl_rate) ++{ ++ struct dcn30_hpo_hdmi_stream_encoder *enc3 = ++ DCN3_0_HPO_HDMI_STREAM_ENC_FROM_HPO_STREAM_ENC(enc); ++ ++ struct frl_audio_clock_info audio_clock_info = { 0 }; ++ ++ /* Setup audio in AFMT - program AFMT block associated with HPO */ ++ ASSERT(enc->afmt); ++ enc->afmt->funcs->setup_hdmi_audio(enc->afmt); ++ ++ REG_UPDATE_3(HDMI_TB_ENC_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1, ++ HDMI_ACR_SOURCE, 0, HDMI_ACR_AUDIO_PRIORITY, 0); ++ ++ /* Program audio clock sample/regeneration parameters */ ++ get_frl_audio_clock_info(&audio_clock_info, frl_rate); ++ ++ REG_UPDATE(HDMI_TB_ENC_ACR_32_0, HDMI_ACR_CTS_32, ++ audio_clock_info.cts_32khz); ++ REG_UPDATE(HDMI_TB_ENC_ACR_32_1, HDMI_ACR_N_32, ++ audio_clock_info.n_32khz); ++ ++ REG_UPDATE(HDMI_TB_ENC_ACR_44_0, HDMI_ACR_CTS_44, ++ audio_clock_info.cts_44khz); ++ REG_UPDATE(HDMI_TB_ENC_ACR_44_1, HDMI_ACR_N_44, ++ audio_clock_info.n_44khz); ++ ++ REG_UPDATE(HDMI_TB_ENC_ACR_48_0, HDMI_ACR_CTS_48, ++ audio_clock_info.cts_48khz); ++ REG_UPDATE(HDMI_TB_ENC_ACR_48_1, HDMI_ACR_N_48, ++ audio_clock_info.n_48khz); ++} ++ ++static void dcn30_hpo_hdmi_stream_enc_hdmi_audio_setup( ++ struct hpo_hdmi_stream_encoder *enc, unsigned int az_inst, ++ struct audio_info *info, struct audio_crtc_info *audio_crtc_info, ++ uint8_t frl_rate) ++{ ++ setup_hdmi_audio(enc, audio_crtc_info, frl_rate); ++ ASSERT(enc->afmt); ++ enc->afmt->funcs->se_audio_setup(enc->afmt, az_inst, info); ++} ++ ++static void ++dcn30_hpo_hdmi_stream_enc_hdmi_audio_enable(struct hpo_hdmi_stream_encoder *enc) ++{ ++ enc->afmt->funcs->audio_mute_control(enc->afmt, false); ++} ++ ++static void dcn30_hpo_hdmi_stream_enc_hdmi_audio_disable( ++ struct hpo_hdmi_stream_encoder *enc) ++{ ++ if (enc->afmt && enc->afmt->funcs->afmt_powerdown) ++ enc->afmt->funcs->afmt_powerdown(enc->afmt); ++} ++ ++static const struct hpo_hdmi_stream_encoder_funcs ++ dcn30_hpo_hdmi_stream_enc_funcs = { ++ .enable = dcn30_hpo_hdmi_stream_enc_enable, ++ .disable = dcn30_hpo_hdmi_stream_enc_disable, ++ .setup_stream_attribute = ++ dcn30_hpo_hdmi_stream_enc_setup_stream_attribute, ++ .update_hdmi_info_packets = ++ dcn30_hpo_hdmi_stream_enc_update_info_packets, ++ .stop_hdmi_info_packets = ++ dcn30_hpo_hdmi_stream_enc_stop_info_packets, ++ .hdmi_audio_setup = dcn30_hpo_hdmi_stream_enc_hdmi_audio_setup, ++ .hdmi_audio_enable = ++ dcn30_hpo_hdmi_stream_enc_hdmi_audio_enable, ++ .hdmi_audio_disable = ++ dcn30_hpo_hdmi_stream_enc_hdmi_audio_disable, ++ }; ++ ++void dcn30_hpo_hdmi_stream_encoder_construct( ++ struct dcn30_hpo_hdmi_stream_encoder *enc, struct dc_context *ctx, ++ uint32_t inst, struct vpg *vpg, struct afmt *afmt, ++ const struct dcn30_hpo_hdmi_stream_encoder_registers *regs, ++ const struct dcn30_hpo_hdmi_stream_encoder_shift *shift, ++ const struct dcn30_hpo_hdmi_stream_encoder_mask *mask) ++{ ++ enc->base.funcs = &dcn30_hpo_hdmi_stream_enc_funcs; ++ enc->base.ctx = ctx; ++ enc->base.inst = inst; ++ enc->base.vpg = vpg; ++ enc->base.afmt = afmt; ++ enc->regs = regs; ++ enc->hpo_se_shift = shift; ++ enc->hpo_se_mask = mask; ++} +diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_hdmi_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_hdmi_stream_encoder.h +new file mode 100644 +index 000000000000..ba97e0c0e346 +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_hdmi_stream_encoder.h +@@ -0,0 +1,768 @@ ++/* ++ * HPO HDMI Stream Encoder ++ * ++ * Copyright 2026 Michał Kopeć ++ */ ++ ++#ifndef __DAL_DCN401_HPO_HDMI_STREAM_ENCODER_H__ ++#define __DAL_DCN401_HPO_HDMI_STREAM_ENCODER_H__ ++ ++#include "dcn30/dcn30_vpg.h" ++#include "dcn30/dcn30_afmt.h" ++#include "stream_encoder.h" ++#include "dcn20/dcn20_stream_encoder.h" ++ ++/* ------------------------------------------------------------------------- */ ++/* Container macro */ ++/* ------------------------------------------------------------------------- */ ++ ++#define DCN3_0_HPO_HDMI_STREAM_ENC_FROM_HPO_STREAM_ENC(hpo_enc) \ ++ container_of(hpo_enc, struct dcn30_hpo_hdmi_stream_encoder, base) ++ ++/* ------------------------------------------------------------------------- */ ++/* Register list */ ++/* ------------------------------------------------------------------------- */ ++ ++#define DCN3_0_HPO_HDMI_STREAM_ENC_REG_LIST() \ ++ /* HPO stream encoder - clock and FIFO control */ \ ++ SR(HDMI_STREAM_ENC_CLOCK_CONTROL), \ ++ SR(HDMI_STREAM_ENC_INPUT_MUX_CONTROL), \ ++ SR(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0), \ ++ SR(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1), \ ++ SR(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2), \ ++ \ ++ /* TB encoder - control and pixel format */ \ ++ SR(HDMI_TB_ENC_CONTROL), SR(HDMI_TB_ENC_PIXEL_FORMAT), \ ++ SR(HDMI_TB_ENC_MODE), SR(HDMI_TB_ENC_DB_CONTROL), \ ++ \ ++ /* TB encoder - packet control */ \ ++ SR(HDMI_TB_ENC_PACKET_CONTROL), \ ++ SR(HDMI_TB_ENC_VBI_PACKET_CONTROL1), \ ++ SR(HDMI_TB_ENC_VBI_PACKET_CONTROL2), \ ++ SR(HDMI_TB_ENC_GC_CONTROL), \ ++ SR(HDMI_TB_ENC_ACR_PACKET_CONTROL), \ ++ \ ++ /* TB encoder - generic packet control (SEND/CONT) */ \ ++ SR(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0), \ ++ SR(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1), \ ++ SR(HDMI_TB_ENC_GENERIC_PACKET_CONTROL2), \ ++ \ ++ /* TB encoder - generic packet line numbers */ \ ++ SR(HDMI_TB_ENC_GENERIC_PACKET0_1_LINE), \ ++ SR(HDMI_TB_ENC_GENERIC_PACKET2_3_LINE), \ ++ SR(HDMI_TB_ENC_GENERIC_PACKET4_5_LINE), \ ++ SR(HDMI_TB_ENC_GENERIC_PACKET6_7_LINE), \ ++ SR(HDMI_TB_ENC_GENERIC_PACKET8_9_LINE), \ ++ SR(HDMI_TB_ENC_GENERIC_PACKET10_11_LINE), \ ++ SR(HDMI_TB_ENC_GENERIC_PACKET12_13_LINE), \ ++ SR(HDMI_TB_ENC_GENERIC_PACKET14_LINE), \ ++ \ ++ /* TB encoder - timing */ \ ++ SR(HDMI_TB_ENC_H_ACTIVE_BLANK), \ ++ SR(HDMI_TB_ENC_HC_ACTIVE_BLANK), \ ++ \ ++ /* TB encoder - ACR */ \ ++ SR(HDMI_TB_ENC_ACR_32_0), SR(HDMI_TB_ENC_ACR_32_1), \ ++ SR(HDMI_TB_ENC_ACR_44_0), SR(HDMI_TB_ENC_ACR_44_1), \ ++ SR(HDMI_TB_ENC_ACR_48_0), SR(HDMI_TB_ENC_ACR_48_1), \ ++ SR(HDMI_TB_ENC_ACR_STATUS_0), SR(HDMI_TB_ENC_ACR_STATUS_1), \ ++ \ ++ /* TB encoder - CRC */ \ ++ SR(HDMI_TB_ENC_CRC_CNTL), SR(HDMI_TB_ENC_CRC_RESULT_0), \ ++ SR(HDMI_TB_ENC_CRC_RESULT_1), \ ++ \ ++ /* TB encoder - memory and buffer control */ \ ++ SR(HDMI_TB_ENC_MEM_CTRL), SR(HDMI_TB_ENC_BUFFER_CONTROL), \ ++ \ ++ /* TB encoder - status */ \ ++ SR(HDMI_TB_ENC_INPUT_FIFO_STATUS) ++ ++/* ------------------------------------------------------------------------- */ ++/* Register storage */ ++/* ------------------------------------------------------------------------- */ ++ ++#define DCN3_0_HPO_HDMI_STREAM_ENC_REGS \ ++ /* HPO stream encoder */ \ ++ uint32_t HDMI_STREAM_ENC_CLOCK_CONTROL; \ ++ uint32_t HDMI_STREAM_ENC_INPUT_MUX_CONTROL; \ ++ uint32_t HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0; \ ++ uint32_t HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1; \ ++ uint32_t HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2; \ ++ /* TB encoder - control */ \ ++ uint32_t HDMI_TB_ENC_CONTROL; \ ++ uint32_t HDMI_TB_ENC_PIXEL_FORMAT; \ ++ uint32_t HDMI_TB_ENC_MODE; \ ++ uint32_t HDMI_TB_ENC_DB_CONTROL; \ ++ /* TB encoder - packets */ \ ++ uint32_t HDMI_TB_ENC_PACKET_CONTROL; \ ++ uint32_t HDMI_TB_ENC_VBI_PACKET_CONTROL1; \ ++ uint32_t HDMI_TB_ENC_VBI_PACKET_CONTROL2; \ ++ uint32_t HDMI_TB_ENC_GC_CONTROL; \ ++ uint32_t HDMI_TB_ENC_ACR_PACKET_CONTROL; \ ++ /* TB encoder - generic packet control */ \ ++ uint32_t HDMI_TB_ENC_GENERIC_PACKET_CONTROL0; \ ++ uint32_t HDMI_TB_ENC_GENERIC_PACKET_CONTROL1; \ ++ uint32_t HDMI_TB_ENC_GENERIC_PACKET_CONTROL2; \ ++ /* TB encoder - generic packet lines */ \ ++ uint32_t HDMI_TB_ENC_GENERIC_PACKET0_1_LINE; \ ++ uint32_t HDMI_TB_ENC_GENERIC_PACKET2_3_LINE; \ ++ uint32_t HDMI_TB_ENC_GENERIC_PACKET4_5_LINE; \ ++ uint32_t HDMI_TB_ENC_GENERIC_PACKET6_7_LINE; \ ++ uint32_t HDMI_TB_ENC_GENERIC_PACKET8_9_LINE; \ ++ uint32_t HDMI_TB_ENC_GENERIC_PACKET10_11_LINE; \ ++ uint32_t HDMI_TB_ENC_GENERIC_PACKET12_13_LINE; \ ++ uint32_t HDMI_TB_ENC_GENERIC_PACKET14_LINE; \ ++ /* TB encoder - timing */ \ ++ uint32_t HDMI_TB_ENC_H_ACTIVE_BLANK; \ ++ uint32_t HDMI_TB_ENC_HC_ACTIVE_BLANK; \ ++ /* TB encoder - ACR */ \ ++ uint32_t HDMI_TB_ENC_ACR_32_0; \ ++ uint32_t HDMI_TB_ENC_ACR_32_1; \ ++ uint32_t HDMI_TB_ENC_ACR_44_0; \ ++ uint32_t HDMI_TB_ENC_ACR_44_1; \ ++ uint32_t HDMI_TB_ENC_ACR_48_0; \ ++ uint32_t HDMI_TB_ENC_ACR_48_1; \ ++ uint32_t HDMI_TB_ENC_ACR_STATUS_0; \ ++ uint32_t HDMI_TB_ENC_ACR_STATUS_1; \ ++ /* TB encoder - CRC */ \ ++ uint32_t HDMI_TB_ENC_CRC_CNTL; \ ++ uint32_t HDMI_TB_ENC_CRC_RESULT_0; \ ++ uint32_t HDMI_TB_ENC_CRC_RESULT_1; \ ++ /* TB encoder - memory and buffer */ \ ++ uint32_t HDMI_TB_ENC_MEM_CTRL; \ ++ uint32_t HDMI_TB_ENC_BUFFER_CONTROL; \ ++ /* TB encoder - status */ \ ++ uint32_t HDMI_TB_ENC_INPUT_FIFO_STATUS; ++ ++struct dcn30_hpo_hdmi_stream_encoder_registers { ++ DCN3_0_HPO_HDMI_STREAM_ENC_REGS; ++}; ++ ++/* ------------------------------------------------------------------------- */ ++/* Field list */ ++/* ------------------------------------------------------------------------- */ ++ ++#define DCN3_0_HPO_HDMI_STREAM_ENC_MASK_SH_LIST(mask_sh) \ ++ /* HDMI_STREAM_ENC_CLOCK_CONTROL */ \ ++ SE_SF(HDMI_STREAM_ENC_CLOCK_CONTROL, HDMI_STREAM_ENC_CLOCK_EN, \ ++ mask_sh), \ ++ SE_SF(HDMI_STREAM_ENC_CLOCK_CONTROL, \ ++ HDMI_STREAM_ENC_CLOCK_ON_DISPCLK, mask_sh), \ ++ SE_SF(HDMI_STREAM_ENC_CLOCK_CONTROL, \ ++ HDMI_STREAM_ENC_CLOCK_ON_SOCCLK, mask_sh), \ ++ SE_SF(HDMI_STREAM_ENC_CLOCK_CONTROL, \ ++ HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK, mask_sh), \ ++ \ ++ /* HDMI_STREAM_ENC_INPUT_MUX_CONTROL */ \ ++ SE_SF(HDMI_STREAM_ENC_INPUT_MUX_CONTROL, \ ++ HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL, mask_sh), \ ++ \ ++ /* HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 */ \ ++ SE_SF(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, \ ++ FIFO_ENABLE, mask_sh), \ ++ SE_SF(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, \ ++ FIFO_RESET, mask_sh), \ ++ SE_SF(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, \ ++ FIFO_PIXEL_ENCODING_TYPE, mask_sh), \ ++ SE_SF(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, \ ++ FIFO_RESET_DONE, mask_sh), \ ++ SE_SF(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, \ ++ FIFO_VIDEO_STREAM_ACTIVE, mask_sh), \ ++ SE_SF(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, \ ++ FIFO_ERROR, mask_sh), \ ++ \ ++ /* HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 */ \ ++ SE_SF(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1, \ ++ FIFO_USE_OVERWRITE_LEVEL, mask_sh), \ ++ SE_SF(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1, \ ++ FIFO_FORCE_RECAL_AVERAGE, mask_sh), \ ++ SE_SF(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1, \ ++ FIFO_FORCE_RECOMP_MINMAX, mask_sh), \ ++ SE_SF(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1, \ ++ FIFO_OVERWRITE_LEVEL, mask_sh), \ ++ SE_SF(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1, \ ++ FIFO_MINIMUM_LEVEL, mask_sh), \ ++ SE_SF(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1, \ ++ FIFO_MAXIMUM_LEVEL, mask_sh), \ ++ SE_SF(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1, \ ++ FIFO_CAL_AVERAGE_LEVEL, mask_sh), \ ++ SE_SF(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1, \ ++ FIFO_CALIBRATED, mask_sh), \ ++ \ ++ /* HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 */ \ ++ SE_SF(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2, \ ++ FIFO_READ_START_LEVEL, mask_sh), \ ++ SE_SF(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2, \ ++ FIFO_READ_CLOCK_SRC, mask_sh), \ ++ \ ++ /* HDMI_TB_ENC_CONTROL */ \ ++ SE_SF(HDMI_TB_ENC_CONTROL, HDMI_TB_ENC_EN, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_CONTROL, HDMI_RESET, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_CONTROL, HDMI_RESET_DONE, mask_sh), \ ++ \ ++ /* HDMI_TB_ENC_PIXEL_FORMAT */ \ ++ SE_SF(HDMI_TB_ENC_PIXEL_FORMAT, HDMI_DEEP_COLOR_ENABLE, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_PIXEL_FORMAT, HDMI_DEEP_COLOR_DEPTH, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_PIXEL_FORMAT, HDMI_PIXEL_ENCODING, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_PIXEL_FORMAT, HDMI_DSC_MODE, mask_sh), \ ++ \ ++ /* HDMI_TB_ENC_MODE */ \ ++ SE_SF(HDMI_TB_ENC_MODE, HDMI_BORROW_MODE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_MODE, HDMI_SKIP_FIRST_HBLANK, mask_sh), \ ++ \ ++ /* HDMI_TB_ENC_DB_CONTROL */ \ ++ SE_SF(HDMI_TB_ENC_DB_CONTROL, HDMI_DB_PENDING, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_DB_CONTROL, HDMI_DB_DISABLE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_DB_CONTROL, VUPDATE_DB_PENDING, mask_sh), \ ++ \ ++ /* HDMI_TB_ENC_PACKET_CONTROL */ \ ++ SE_SF(HDMI_TB_ENC_PACKET_CONTROL, HDMI_MAX_PACKETS_PER_LINE, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_PACKET_CONTROL, HDMI_MAX_ISLANDS_PER_LINE, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_PACKET_CONTROL, HDMI_ACR_AUTO_SEND_OVERFLOW, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_PACKET_CONTROL, \ ++ HDMI_TB_ENC_PACKET_ERROR_CLEAR, mask_sh), \ ++ \ ++ /* HDMI_TB_ENC_VBI_PACKET_CONTROL1 */ \ ++ SE_SF(HDMI_TB_ENC_VBI_PACKET_CONTROL1, HDMI_GC_SEND, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_VBI_PACKET_CONTROL1, HDMI_GC_CONT, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_VBI_PACKET_CONTROL1, HDMI_ISRC_SEND, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_VBI_PACKET_CONTROL1, HDMI_ISRC_CONT, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_VBI_PACKET_CONTROL1, HDMI_ACP_SEND, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_VBI_PACKET_CONTROL1, HDMI_AUDIO_INFO_SEND, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_VBI_PACKET_CONTROL1, HDMI_AUDIO_INFO_CONT, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_VBI_PACKET_CONTROL1, HDMI_AUDIO_INFO_LINE, \ ++ mask_sh), \ ++ \ ++ /* HDMI_TB_ENC_VBI_PACKET_CONTROL2 */ \ ++ SE_SF(HDMI_TB_ENC_VBI_PACKET_CONTROL2, HDMI_ISRC_LINE, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_VBI_PACKET_CONTROL2, HDMI_ACP_LINE, \ ++ mask_sh), \ ++ \ ++ /* HDMI_TB_ENC_GC_CONTROL */ \ ++ SE_SF(HDMI_TB_ENC_GC_CONTROL, HDMI_GC_AVMUTE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GC_CONTROL, HDMI_GC_AVMUTE_CONT, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GC_CONTROL, HDMI_DEFAULT_PHASE, mask_sh), \ ++ \ ++ /* HDMI_TB_ENC_ACR_PACKET_CONTROL */ \ ++ SE_SF(HDMI_TB_ENC_ACR_PACKET_CONTROL, HDMI_ACR_SEND, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_ACR_PACKET_CONTROL, HDMI_ACR_CONT, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_ACR_PACKET_CONTROL, HDMI_ACR_SELECT, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_ACR_PACKET_CONTROL, HDMI_ACR_N_MULTIPLE, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, \ ++ mask_sh), \ ++ \ ++ /* HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 - packets 0-7 SEND/CONT */ \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, \ ++ HDMI_GENERIC0_LOCK_EN, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, \ ++ HDMI_GENERIC0_LINE_REFERENCE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, \ ++ HDMI_GENERIC1_LOCK_EN, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, \ ++ HDMI_GENERIC1_LINE_REFERENCE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_SEND, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_CONT, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, \ ++ HDMI_GENERIC2_LOCK_EN, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, \ ++ HDMI_GENERIC2_LINE_REFERENCE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_SEND, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_CONT, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, \ ++ HDMI_GENERIC3_LOCK_EN, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, \ ++ HDMI_GENERIC3_LINE_REFERENCE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_SEND, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_CONT, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, \ ++ HDMI_GENERIC4_LOCK_EN, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, \ ++ HDMI_GENERIC4_LINE_REFERENCE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_SEND, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_CONT, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, \ ++ HDMI_GENERIC5_LOCK_EN, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, \ ++ HDMI_GENERIC5_LINE_REFERENCE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_SEND, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_CONT, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, \ ++ HDMI_GENERIC6_LOCK_EN, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, \ ++ HDMI_GENERIC6_LINE_REFERENCE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_SEND, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_CONT, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, \ ++ HDMI_GENERIC7_LOCK_EN, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, \ ++ HDMI_GENERIC7_LINE_REFERENCE, mask_sh), \ ++ \ ++ /* HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 - packets 8-14 SEND/CONT */ \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, HDMI_GENERIC8_SEND, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, HDMI_GENERIC8_CONT, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC8_LOCK_EN, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC8_LINE_REFERENCE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, HDMI_GENERIC9_SEND, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, HDMI_GENERIC9_CONT, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC9_LOCK_EN, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC9_LINE_REFERENCE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC10_SEND, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC10_CONT, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC10_LOCK_EN, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC10_LINE_REFERENCE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC11_SEND, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC11_CONT, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC11_LOCK_EN, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC11_LINE_REFERENCE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC12_SEND, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC12_CONT, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC12_LOCK_EN, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC12_LINE_REFERENCE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC13_SEND, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC13_CONT, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC13_LOCK_EN, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC13_LINE_REFERENCE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC14_SEND, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC14_CONT, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC14_LOCK_EN, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, \ ++ HDMI_GENERIC14_LINE_REFERENCE, mask_sh), \ ++ \ ++ /* HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 - immediate send */ \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL2, \ ++ HDMI_GENERIC0_IMMEDIATE_SEND, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL2, \ ++ HDMI_GENERIC1_IMMEDIATE_SEND, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL2, \ ++ HDMI_GENERIC2_IMMEDIATE_SEND, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL2, \ ++ HDMI_GENERIC3_IMMEDIATE_SEND, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL2, \ ++ HDMI_GENERIC4_IMMEDIATE_SEND, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL2, \ ++ HDMI_GENERIC5_IMMEDIATE_SEND, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL2, \ ++ HDMI_GENERIC6_IMMEDIATE_SEND, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL2, \ ++ HDMI_GENERIC7_IMMEDIATE_SEND, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL2, \ ++ HDMI_GENERIC8_IMMEDIATE_SEND, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL2, \ ++ HDMI_GENERIC9_IMMEDIATE_SEND, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL2, \ ++ HDMI_GENERIC10_IMMEDIATE_SEND, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL2, \ ++ HDMI_GENERIC11_IMMEDIATE_SEND, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL2, \ ++ HDMI_GENERIC12_IMMEDIATE_SEND, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL2, \ ++ HDMI_GENERIC13_IMMEDIATE_SEND, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET_CONTROL2, \ ++ HDMI_GENERIC14_IMMEDIATE_SEND, mask_sh), \ ++ \ ++ /* HDMI_TB_ENC_GENERIC_PACKET line registers */ \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET0_1_LINE, HDMI_GENERIC0_LINE, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET0_1_LINE, HDMI_GENERIC0_EMP, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET0_1_LINE, HDMI_GENERIC1_LINE, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET0_1_LINE, HDMI_GENERIC1_EMP, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET2_3_LINE, HDMI_GENERIC2_LINE, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET2_3_LINE, HDMI_GENERIC2_EMP, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET2_3_LINE, HDMI_GENERIC3_LINE, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET2_3_LINE, HDMI_GENERIC3_EMP, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET4_5_LINE, HDMI_GENERIC4_LINE, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET4_5_LINE, HDMI_GENERIC4_EMP, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET4_5_LINE, HDMI_GENERIC5_LINE, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET4_5_LINE, HDMI_GENERIC5_EMP, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET6_7_LINE, HDMI_GENERIC6_LINE, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET6_7_LINE, HDMI_GENERIC6_EMP, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET6_7_LINE, HDMI_GENERIC7_LINE, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET6_7_LINE, HDMI_GENERIC7_EMP, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET8_9_LINE, HDMI_GENERIC8_LINE, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET8_9_LINE, HDMI_GENERIC8_EMP, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET8_9_LINE, HDMI_GENERIC9_LINE, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET8_9_LINE, HDMI_GENERIC9_EMP, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET10_11_LINE, \ ++ HDMI_GENERIC10_LINE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET10_11_LINE, \ ++ HDMI_GENERIC10_EMP, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET10_11_LINE, \ ++ HDMI_GENERIC11_LINE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET10_11_LINE, \ ++ HDMI_GENERIC11_EMP, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET12_13_LINE, \ ++ HDMI_GENERIC12_LINE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET12_13_LINE, \ ++ HDMI_GENERIC12_EMP, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET12_13_LINE, \ ++ HDMI_GENERIC13_LINE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET12_13_LINE, \ ++ HDMI_GENERIC13_EMP, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET14_LINE, HDMI_GENERIC14_LINE, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_GENERIC_PACKET14_LINE, HDMI_GENERIC14_EMP, \ ++ mask_sh), \ ++ \ ++ /* HDMI_TB_ENC_H_ACTIVE_BLANK */ \ ++ SE_SF(HDMI_TB_ENC_H_ACTIVE_BLANK, HDMI_H_ACTIVE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_H_ACTIVE_BLANK, HDMI_H_BLANK, mask_sh), \ ++ \ ++ /* HDMI_TB_ENC_HC_ACTIVE_BLANK */ \ ++ SE_SF(HDMI_TB_ENC_HC_ACTIVE_BLANK, HDMI_HC_ACTIVE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_HC_ACTIVE_BLANK, HDMI_HC_BLANK, mask_sh), \ ++ \ ++ /* HDMI_TB_ENC_ACR registers */ \ ++ SE_SF(HDMI_TB_ENC_ACR_32_0, HDMI_ACR_CTS_32, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_ACR_32_1, HDMI_ACR_N_32, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_ACR_44_0, HDMI_ACR_CTS_44, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_ACR_44_1, HDMI_ACR_N_44, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_ACR_48_0, HDMI_ACR_CTS_48, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_ACR_48_1, HDMI_ACR_N_48, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_ACR_STATUS_0, HDMI_ACR_CTS, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_ACR_STATUS_1, HDMI_ACR_N, mask_sh), \ ++ \ ++ /* HDMI_TB_ENC_CRC_CNTL */ \ ++ SE_SF(HDMI_TB_ENC_CRC_CNTL, HDMI_CRC_EN, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_CRC_CNTL, HDMI_CRC_CONT_EN, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_CRC_CNTL, HDMI_CRC_TYPE, mask_sh), \ ++ SE_SF(HDMI_TB_ENC_CRC_CNTL, HDMI_CRC_SRC_SEL, mask_sh), \ ++ \ ++ /* HDMI_TB_ENC_MEM_CTRL */ \ ++ SE_SF(HDMI_TB_ENC_MEM_CTRL, BORROWBUFFER_MEM_PWR_DIS, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_MEM_CTRL, BORROWBUFFER_MEM_PWR_FORCE, \ ++ mask_sh), \ ++ SE_SF(HDMI_TB_ENC_MEM_CTRL, BORROWBUFFER_MEM_PWR_STATE, \ ++ mask_sh), \ ++ \ ++ /* HDMI_TB_ENC_INPUT_FIFO_STATUS */ \ ++ SE_SF(HDMI_TB_ENC_INPUT_FIFO_STATUS, INPUT_FIFO_ERROR, \ ++ mask_sh) ++ ++/* ------------------------------------------------------------------------- */ ++/* Register field list for shift/mask structs */ ++/* ------------------------------------------------------------------------- */ ++ ++#define DCN3_0_HPO_HDMI_STREAM_ENC_REG_FIELD_LIST(type) \ ++ /* Stream encoder clock/FIFO */ \ ++ type HDMI_STREAM_ENC_CLOCK_EN; \ ++ type HDMI_STREAM_ENC_CLOCK_ON_DISPCLK; \ ++ type HDMI_STREAM_ENC_CLOCK_ON_SOCCLK; \ ++ type HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK; \ ++ type HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL; \ ++ type FIFO_ENABLE; \ ++ type FIFO_RESET; \ ++ type FIFO_PIXEL_ENCODING_TYPE; \ ++ type FIFO_UNCOMPRESSED_PIXEL_FORMAT; \ ++ type FIFO_COMPRESSED_PIXEL_FORMAT; \ ++ type FIFO_RESET_DONE; \ ++ type FIFO_VIDEO_STREAM_ACTIVE; \ ++ type FIFO_ERROR; \ ++ type FIFO_USE_OVERWRITE_LEVEL; \ ++ type FIFO_FORCE_RECAL_AVERAGE; \ ++ type FIFO_FORCE_RECOMP_MINMAX; \ ++ type FIFO_OVERWRITE_LEVEL; \ ++ type FIFO_MINIMUM_LEVEL; \ ++ type FIFO_MAXIMUM_LEVEL; \ ++ type FIFO_CAL_AVERAGE_LEVEL; \ ++ type FIFO_CALIBRATED; \ ++ type FIFO_READ_START_LEVEL; \ ++ type FIFO_READ_CLOCK_SRC; \ ++ /* TB encoder control */ \ ++ type HDMI_TB_ENC_EN; \ ++ type HDMI_RESET; \ ++ type HDMI_RESET_DONE; \ ++ /* TB encoder pixel format */ \ ++ type HDMI_DEEP_COLOR_ENABLE; \ ++ type HDMI_DEEP_COLOR_DEPTH; \ ++ type HDMI_PIXEL_ENCODING; \ ++ type HDMI_DSC_MODE; \ ++ /* TB encoder mode */ \ ++ type HDMI_BORROW_MODE; \ ++ type HDMI_SKIP_FIRST_HBLANK; \ ++ /* TB encoder DB control */ \ ++ type HDMI_DB_PENDING; \ ++ type HDMI_DB_DISABLE; \ ++ type VUPDATE_DB_PENDING; \ ++ /* TB encoder packet control */ \ ++ type HDMI_MAX_PACKETS_PER_LINE; \ ++ type HDMI_MAX_ISLANDS_PER_LINE; \ ++ type HDMI_ACR_AUTO_SEND_OVERFLOW; \ ++ type HDMI_TB_ENC_PACKET_ERROR_CLEAR; \ ++ /* TB encoder VBI packet control */ \ ++ type HDMI_GC_SEND; \ ++ type HDMI_GC_CONT; \ ++ type HDMI_ISRC_SEND; \ ++ type HDMI_ISRC_CONT; \ ++ type HDMI_ACP_SEND; \ ++ type HDMI_AUDIO_INFO_SEND; \ ++ type HDMI_AUDIO_INFO_CONT; \ ++ type HDMI_AUDIO_INFO_LINE; \ ++ type HDMI_ISRC_LINE; \ ++ type HDMI_ACP_LINE; \ ++ /* TB encoder GC control */ \ ++ type HDMI_GC_AVMUTE; \ ++ type HDMI_GC_AVMUTE_CONT; \ ++ type HDMI_DEFAULT_PHASE; \ ++ /* TB encoder ACR packet control */ \ ++ type HDMI_ACR_SEND; \ ++ type HDMI_ACR_CONT; \ ++ type HDMI_ACR_SELECT; \ ++ type HDMI_ACR_SOURCE; \ ++ type HDMI_ACR_AUTO_SEND; \ ++ type HDMI_ACR_N_MULTIPLE; \ ++ type HDMI_ACR_AUDIO_PRIORITY; \ ++ /* Generic packet SEND/CONT - packets 0-7 (CONTROL0) */ \ ++ type HDMI_GENERIC0_SEND; \ ++ type HDMI_GENERIC0_CONT; \ ++ type HDMI_GENERIC0_LOCK_EN; \ ++ type HDMI_GENERIC0_LINE_REFERENCE; \ ++ type HDMI_GENERIC1_SEND; \ ++ type HDMI_GENERIC1_CONT; \ ++ type HDMI_GENERIC1_LOCK_EN; \ ++ type HDMI_GENERIC1_LINE_REFERENCE; \ ++ type HDMI_GENERIC2_SEND; \ ++ type HDMI_GENERIC2_CONT; \ ++ type HDMI_GENERIC2_LOCK_EN; \ ++ type HDMI_GENERIC2_LINE_REFERENCE; \ ++ type HDMI_GENERIC3_SEND; \ ++ type HDMI_GENERIC3_CONT; \ ++ type HDMI_GENERIC3_LOCK_EN; \ ++ type HDMI_GENERIC3_LINE_REFERENCE; \ ++ type HDMI_GENERIC4_SEND; \ ++ type HDMI_GENERIC4_CONT; \ ++ type HDMI_GENERIC4_LOCK_EN; \ ++ type HDMI_GENERIC4_LINE_REFERENCE; \ ++ type HDMI_GENERIC5_SEND; \ ++ type HDMI_GENERIC5_CONT; \ ++ type HDMI_GENERIC5_LOCK_EN; \ ++ type HDMI_GENERIC5_LINE_REFERENCE; \ ++ type HDMI_GENERIC6_SEND; \ ++ type HDMI_GENERIC6_CONT; \ ++ type HDMI_GENERIC6_LOCK_EN; \ ++ type HDMI_GENERIC6_LINE_REFERENCE; \ ++ type HDMI_GENERIC7_SEND; \ ++ type HDMI_GENERIC7_CONT; \ ++ type HDMI_GENERIC7_LOCK_EN; \ ++ type HDMI_GENERIC7_LINE_REFERENCE; \ ++ /* Generic packet SEND/CONT - packets 8-14 (CONTROL1) */ \ ++ type HDMI_GENERIC8_SEND; \ ++ type HDMI_GENERIC8_CONT; \ ++ type HDMI_GENERIC8_LOCK_EN; \ ++ type HDMI_GENERIC8_LINE_REFERENCE; \ ++ type HDMI_GENERIC9_SEND; \ ++ type HDMI_GENERIC9_CONT; \ ++ type HDMI_GENERIC9_LOCK_EN; \ ++ type HDMI_GENERIC9_LINE_REFERENCE; \ ++ type HDMI_GENERIC10_SEND; \ ++ type HDMI_GENERIC10_CONT; \ ++ type HDMI_GENERIC10_LOCK_EN; \ ++ type HDMI_GENERIC10_LINE_REFERENCE; \ ++ type HDMI_GENERIC11_SEND; \ ++ type HDMI_GENERIC11_CONT; \ ++ type HDMI_GENERIC11_LOCK_EN; \ ++ type HDMI_GENERIC11_LINE_REFERENCE; \ ++ type HDMI_GENERIC12_SEND; \ ++ type HDMI_GENERIC12_CONT; \ ++ type HDMI_GENERIC12_LOCK_EN; \ ++ type HDMI_GENERIC12_LINE_REFERENCE; \ ++ type HDMI_GENERIC13_SEND; \ ++ type HDMI_GENERIC13_CONT; \ ++ type HDMI_GENERIC13_LOCK_EN; \ ++ type HDMI_GENERIC13_LINE_REFERENCE; \ ++ type HDMI_GENERIC14_SEND; \ ++ type HDMI_GENERIC14_CONT; \ ++ type HDMI_GENERIC14_LOCK_EN; \ ++ type HDMI_GENERIC14_LINE_REFERENCE; \ ++ /* Generic packet immediate send (CONTROL2) */ \ ++ type HDMI_GENERIC0_IMMEDIATE_SEND; \ ++ type HDMI_GENERIC1_IMMEDIATE_SEND; \ ++ type HDMI_GENERIC2_IMMEDIATE_SEND; \ ++ type HDMI_GENERIC3_IMMEDIATE_SEND; \ ++ type HDMI_GENERIC4_IMMEDIATE_SEND; \ ++ type HDMI_GENERIC5_IMMEDIATE_SEND; \ ++ type HDMI_GENERIC6_IMMEDIATE_SEND; \ ++ type HDMI_GENERIC7_IMMEDIATE_SEND; \ ++ type HDMI_GENERIC8_IMMEDIATE_SEND; \ ++ type HDMI_GENERIC9_IMMEDIATE_SEND; \ ++ type HDMI_GENERIC10_IMMEDIATE_SEND; \ ++ type HDMI_GENERIC11_IMMEDIATE_SEND; \ ++ type HDMI_GENERIC12_IMMEDIATE_SEND; \ ++ type HDMI_GENERIC13_IMMEDIATE_SEND; \ ++ type HDMI_GENERIC14_IMMEDIATE_SEND; \ ++ /* Generic packet line numbers */ \ ++ type HDMI_GENERIC0_LINE; \ ++ type HDMI_GENERIC0_EMP; \ ++ type HDMI_GENERIC1_LINE; \ ++ type HDMI_GENERIC1_EMP; \ ++ type HDMI_GENERIC2_LINE; \ ++ type HDMI_GENERIC2_EMP; \ ++ type HDMI_GENERIC3_LINE; \ ++ type HDMI_GENERIC3_EMP; \ ++ type HDMI_GENERIC4_LINE; \ ++ type HDMI_GENERIC4_EMP; \ ++ type HDMI_GENERIC5_LINE; \ ++ type HDMI_GENERIC5_EMP; \ ++ type HDMI_GENERIC6_LINE; \ ++ type HDMI_GENERIC6_EMP; \ ++ type HDMI_GENERIC7_LINE; \ ++ type HDMI_GENERIC7_EMP; \ ++ type HDMI_GENERIC8_LINE; \ ++ type HDMI_GENERIC8_EMP; \ ++ type HDMI_GENERIC9_LINE; \ ++ type HDMI_GENERIC9_EMP; \ ++ type HDMI_GENERIC10_LINE; \ ++ type HDMI_GENERIC10_EMP; \ ++ type HDMI_GENERIC11_LINE; \ ++ type HDMI_GENERIC11_EMP; \ ++ type HDMI_GENERIC12_LINE; \ ++ type HDMI_GENERIC12_EMP; \ ++ type HDMI_GENERIC13_LINE; \ ++ type HDMI_GENERIC13_EMP; \ ++ type HDMI_GENERIC14_LINE; \ ++ type HDMI_GENERIC14_EMP; \ ++ /* TB encoder timing */ \ ++ type HDMI_H_ACTIVE; \ ++ type HDMI_H_BLANK; \ ++ type HDMI_HC_ACTIVE; \ ++ type HDMI_HC_BLANK; \ ++ /* TB encoder ACR values */ \ ++ type HDMI_ACR_CTS_32; \ ++ type HDMI_ACR_N_32; \ ++ type HDMI_ACR_CTS_44; \ ++ type HDMI_ACR_N_44; \ ++ type HDMI_ACR_CTS_48; \ ++ type HDMI_ACR_N_48; \ ++ type HDMI_ACR_CTS; \ ++ type HDMI_ACR_N; \ ++ /* TB encoder CRC */ \ ++ type HDMI_CRC_EN; \ ++ type HDMI_CRC_CONT_EN; \ ++ type HDMI_CRC_TYPE; \ ++ type HDMI_CRC_SRC_SEL; \ ++ /* TB encoder memory control */ \ ++ type BORROWBUFFER_MEM_PWR_DIS; \ ++ type BORROWBUFFER_MEM_PWR_FORCE; \ ++ type BORROWBUFFER_MEM_PWR_STATE; \ ++ /* TB encoder status */ \ ++ type INPUT_FIFO_ERROR; ++ ++/* ------------------------------------------------------------------------- */ ++/* Shift / mask tables */ ++/* ------------------------------------------------------------------------- */ ++ ++struct dcn30_hpo_hdmi_stream_encoder_shift { ++ DCN3_0_HPO_HDMI_STREAM_ENC_REG_FIELD_LIST(uint8_t); ++}; ++ ++struct dcn30_hpo_hdmi_stream_encoder_mask { ++ DCN3_0_HPO_HDMI_STREAM_ENC_REG_FIELD_LIST(uint32_t); ++}; ++ ++/* ------------------------------------------------------------------------- */ ++/* Main object */ ++/* ------------------------------------------------------------------------- */ ++ ++struct dcn30_hpo_hdmi_stream_encoder { ++ struct hpo_hdmi_stream_encoder base; ++ ++ const struct dcn30_hpo_hdmi_stream_encoder_registers *regs; ++ const struct dcn30_hpo_hdmi_stream_encoder_shift *hpo_se_shift; ++ const struct dcn30_hpo_hdmi_stream_encoder_mask *hpo_se_mask; ++}; ++ ++/* ------------------------------------------------------------------------- */ ++/* Constructor */ ++/* ------------------------------------------------------------------------- */ ++ ++void dcn30_hpo_hdmi_stream_encoder_construct( ++ struct dcn30_hpo_hdmi_stream_encoder *enc, struct dc_context *ctx, ++ uint32_t inst, struct vpg *vpg, struct afmt *afmt, ++ const struct dcn30_hpo_hdmi_stream_encoder_registers *regs, ++ const struct dcn30_hpo_hdmi_stream_encoder_shift *shift, ++ const struct dcn30_hpo_hdmi_stream_encoder_mask *mask); ++ ++#endif /* __DAL_DCN401_HPO_HDMI_STREAM_ENCODER_H__ */ +\ No newline at end of file +diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +index 4659e1b489ba..2a4732dc7540 100644 +--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +@@ -1159,6 +1159,7 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) + struct timing_generator *tg = pipe_ctx->stream_res.tg; + struct dtbclk_dto_params dto_params = {0}; + int dp_hpo_inst; ++ int hdmi_hpo_inst; + struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; + struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; + +@@ -1170,6 +1171,9 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) + pipe_ctx->stream_res.stream_enc); + pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute( + pipe_ctx->stream_res.stream_enc); ++ } else if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) { ++ pipe_ctx->stream_res.hpo_hdmi_stream_enc->funcs->stop_hdmi_info_packets( ++ pipe_ctx->stream_res.hpo_hdmi_stream_enc); + } + + if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { +@@ -1195,6 +1199,17 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) + dccg->funcs->set_dtbclk_dto(dccg, &dto_params); + } + } ++ } else if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal) && dccg) { ++ dto_params.otg_inst = tg->inst; ++ dto_params.timing = &pipe_ctx->stream->timing; ++ hdmi_hpo_inst = pipe_ctx->stream_res.hpo_hdmi_stream_enc->inst; ++ if (dccg) { ++ dccg->funcs->set_hdmistreamclk(dccg, REFCLK, tg->inst, hdmi_hpo_inst); ++ if (!(dc->ctx->dce_version >= DCN_VERSION_3_5)) { ++ if (dccg && dccg->funcs->set_dtbclk_dto) ++ dccg->funcs->set_dtbclk_dto(dccg, &dto_params); ++ } ++ } + } else if (dccg && dccg->funcs->disable_symclk_se) { + dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst, + link_enc->transmitter - TRANSMITTER_UNIPHY_A); +@@ -1459,7 +1474,8 @@ void build_audio_output( + + if (state->clk_mgr && + (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || +- pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) { ++ pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || ++ pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_FRL)) { + audio_output->pll_info.audio_dto_source_clock_in_khz = + state->clk_mgr->funcs->get_dp_ref_clk_frequency( + state->clk_mgr); +@@ -2427,7 +2443,7 @@ static void dce110_setup_audio_dto( + + if (pipe_ctx->top_pipe) + continue; +- if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) ++ if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) + continue; + if (pipe_ctx->stream_res.audio != NULL) { + struct audio_output audio_output; +diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +index a76436dcbe40..39df7785355c 100644 +--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +@@ -893,7 +893,7 @@ enum dc_status dcn20_enable_stream_timing( + return DC_ERROR_UNEXPECTED; + } + +- if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { ++ if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) || dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) { + struct dccg *dccg = dc->res_pool->dccg; + struct timing_generator *tg = pipe_ctx->stream_res.tg; + struct dtbclk_dto_params dto_params = {0}; +@@ -3035,6 +3035,7 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) + struct dccg *dccg = dc->res_pool->dccg; + enum phyd32clk_clock_source phyd32clk; + int dp_hpo_inst; ++ int hdmi_hpo_inst = 0; + + struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; + struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; +@@ -3058,6 +3059,15 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) + } else { + dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); + } ++ } else if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) { ++ dto_params.otg_inst = tg->inst; ++ dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10; ++ dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx); ++ dto_params.timing = &pipe_ctx->stream->timing; ++ dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); ++ dccg->funcs->set_dtbclk_dto(dccg, &dto_params); ++ hdmi_hpo_inst = pipe_ctx->stream_res.hpo_hdmi_stream_enc->inst; ++ dccg->funcs->set_hdmistreamclk(dccg, DTBCLK0, tg->inst, hdmi_hpo_inst); + } else { + if (dccg->funcs->enable_symclk_se && link_enc) { + if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA +diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +index 2adbcc105aa6..4d0097b3b363 100644 +--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +@@ -379,6 +379,7 @@ void dcn31_enable_power_gating_plane( + void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) + { + bool is_hdmi_tmds; ++ bool is_hdmi_frl; + bool is_dp; + + ASSERT(pipe_ctx->stream); +@@ -387,16 +388,22 @@ void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) + return; /* this is not root pipe */ + + is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); ++ is_hdmi_frl = dc_is_hdmi_frl_signal(pipe_ctx->stream->signal); + is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); + +- if (!is_hdmi_tmds && !is_dp) ++ if (!is_hdmi_tmds && !is_hdmi_frl && !is_dp) + return; + +- if (is_hdmi_tmds) ++ if (is_hdmi_tmds) { + pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( + pipe_ctx->stream_res.stream_enc, + &pipe_ctx->stream_res.encoder_info_frame); +- else if (pipe_ctx->stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { ++ } else if (is_hdmi_frl) { ++ if (pipe_ctx->stream_res.hpo_hdmi_stream_enc->funcs->update_hdmi_info_packets) ++ pipe_ctx->stream_res.hpo_hdmi_stream_enc->funcs->update_hdmi_info_packets( ++ pipe_ctx->stream_res.hpo_hdmi_stream_enc, ++ &pipe_ctx->stream_res.encoder_info_frame); ++ } else if (pipe_ctx->stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { + if (pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num) + pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num( + pipe_ctx->stream_res.hpo_dp_stream_enc, +diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c +index 3e239124c17d..83796ef35ade 100644 +--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c +@@ -191,6 +191,11 @@ void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx + pipe_ctx->stream_res.tg->funcs->set_odm_bypass( + pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); + ++ /* no idea if this is the correct logic. but windows seems to pick manual mode */ ++ if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) ++ pipe_ctx->stream_res.tg->funcs->set_h_timing_div_manual_mode( ++ pipe_ctx->stream_res.tg, true); ++ + if (mpc->funcs->set_out_rate_control) { + for (i = 0; i < opp_cnt; ++i) { + mpc->funcs->set_out_rate_control( +@@ -334,7 +339,7 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig + two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing); + odm_combine_factor = get_odm_config(pipe_ctx, NULL); + +- if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { ++ if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) || dc_is_hdmi_frl_signal(stream->signal)) { + *k1_div = PIXEL_RATE_DIV_BY_1; + *k2_div = PIXEL_RATE_DIV_BY_1; + } else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) { +diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +index 518794fad9e1..d6618275654f 100644 +--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +@@ -1154,6 +1154,11 @@ void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx * + pipe_ctx->stream_res.tg->funcs->set_odm_bypass( + pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); + ++ /* no idea if this is the correct logic. but windows seems to pick manual mode */ ++ if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) ++ pipe_ctx->stream_res.tg->funcs->set_h_timing_div_manual_mode( ++ pipe_ctx->stream_res.tg, true); ++ + for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { + odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( + odm_pipe->stream_res.opp, +@@ -1197,7 +1202,7 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsign + two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing); + odm_combine_factor = get_odm_config(pipe_ctx, NULL); + +- if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { ++ if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) || dc_is_hdmi_frl_signal(stream->signal)) { + *k1_div = PIXEL_RATE_DIV_BY_1; + *k2_div = PIXEL_RATE_DIV_BY_1; + } else if (dc_is_hdmi_tmds_signal(stream->signal) || dc_is_dvi_signal(stream->signal)) { +diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +index f7e16fee7594..10e0c0ac46c7 100644 +--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +@@ -919,7 +919,7 @@ void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx + void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, + struct pg_block_update *update_state) + { +- bool hpo_frl_stream_enc_acquired = false; ++ bool hpo_frl_stream_enc_acquired = true; // HACK + bool hpo_dp_stream_enc_acquired = false; + int i = 0, j = 0; + int edp_num = 0; +diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +index 39b6f6d2d7c1..b9ac6f433d0a 100644 +--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +@@ -907,6 +907,7 @@ static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link) + static void dcn401_enable_stream_calc( + struct pipe_ctx *pipe_ctx, + int *dp_hpo_inst, ++ int *hdmi_hpo_inst, + enum phyd32clk_clock_source *phyd32clk, + unsigned int *tmds_div, + uint32_t *early_control) +@@ -923,6 +924,9 @@ static void dcn401_enable_stream_calc( + *phyd32clk = get_phyd32clk_src(pipe_ctx->stream->link); + } + ++ if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) ++ *hdmi_hpo_inst = pipe_ctx->stream_res.hpo_hdmi_stream_enc->inst; ++ + if (dc_is_tmds_signal(pipe_ctx->stream->signal)) + dcn401_calculate_dccg_tmds_div_value(pipe_ctx, tmds_div); + else +@@ -952,6 +956,7 @@ void dcn401_enable_stream(struct pipe_ctx *pipe_ctx) + struct dccg *dccg = dc->res_pool->dccg; + enum phyd32clk_clock_source phyd32clk = PHYD32CLKA; + int dp_hpo_inst = 0; ++ int hdmi_hpo_inst = 0; + unsigned int tmds_div = PIXEL_RATE_DIV_NA; + unsigned int unused_div = PIXEL_RATE_DIV_NA; + struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; +@@ -960,7 +965,7 @@ void dcn401_enable_stream(struct pipe_ctx *pipe_ctx) + if (!dc->config.unify_link_enc_assignment) + link_enc = link_enc_cfg_get_link_enc(link); + +- dcn401_enable_stream_calc(pipe_ctx, &dp_hpo_inst, &phyd32clk, ++ dcn401_enable_stream_calc(pipe_ctx, &dp_hpo_inst, &hdmi_hpo_inst, &phyd32clk, + &tmds_div, &early_control); + + if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) { +@@ -975,6 +980,8 @@ void dcn401_enable_stream(struct pipe_ctx *pipe_ctx) + dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst, + link_enc->transmitter - TRANSMITTER_UNIPHY_A); + } ++ } else if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) { ++ dccg->funcs->set_hdmistreamclk(dccg, DPREFCLK, tg->inst, hdmi_hpo_inst); + } + + if (dc->res_pool->dccg->funcs->set_pixel_rate_div) { +diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +index 51b0f0fd8fcd..7b17c23521cc 100644 +--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +@@ -1184,6 +1184,10 @@ struct hw_sequencer_funcs { + const struct link_resource *link_res, + enum clock_source_id clock_source, + uint32_t pixel_clock); ++ void (*enable_frl_link_output)(struct dc_link *link, ++ const struct link_resource *link_res, ++ enum dc_color_depth color_depth, ++ uint32_t pixel_clock); + void (*disable_link_output)(struct dc_link *link, + const struct link_resource *link_res, + enum signal_type signal); +diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h +index 82085d9c3f40..b6e60b1e53d3 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h +@@ -60,6 +60,7 @@ enum dc_status { + DC_FAIL_DP_LINK_BANDWIDTH = 28, + DC_FAIL_HW_CURSOR_SUPPORT = 29, + DC_FAIL_DP_TUNNEL_BW_VALIDATE = 30, ++ DC_FAIL_FRL_LINK_BANDWIDTH = 31, + DC_ERROR_UNEXPECTED = -1 + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +index 61d8ef759aca..da8f2db12a72 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +@@ -286,6 +286,12 @@ struct resource_pool { + struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS]; + unsigned int hpo_dp_link_enc_count; + struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS]; ++ ++ unsigned int hpo_hdmi_stream_enc_count; ++ struct hpo_hdmi_stream_encoder *hpo_hdmi_stream_enc[1]; ++ unsigned int hpo_hdmi_link_enc_count; ++ struct hpo_hdmi_link_encoder *hpo_hdmi_link_enc[1]; ++ + struct dc_3dlut *mpc_lut[MAX_PIPES]; + struct dc_transfer_func *mpc_shaper[MAX_PIPES]; + struct dc_rmcm_3dlut rmcm_3dlut[MAX_RMCM_INST]; +@@ -349,6 +355,7 @@ struct stream_resource { + struct timing_generator *tg; + struct stream_encoder *stream_enc; + struct hpo_dp_stream_encoder *hpo_dp_stream_enc; ++ struct hpo_hdmi_stream_encoder *hpo_hdmi_stream_enc; + struct audio *audio; + + struct pixel_clk_params pix_clk_params; +@@ -391,6 +398,7 @@ struct plane_resource { + struct link_resource { + struct link_encoder *dio_link_enc; + struct hpo_dp_link_encoder *hpo_dp_link_enc; ++ struct hpo_hdmi_link_encoder *hpo_hdmi_link_enc; + }; + + struct link_config { +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +index 1e6ffd86a4c0..89592d6b58b5 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +@@ -235,6 +235,12 @@ struct dccg_funcs { + int otg_inst, + int dp_hpo_inst); + ++ void (*set_hdmistreamclk)( ++ struct dccg *dccg, ++ enum streamclk_source src, ++ int otg_inst, ++ int hdmi_hpo_inst); ++ + void (*enable_symclk32_se)( + struct dccg *dccg, + int hpo_se_inst, +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +index a61d12ec61bc..e641ecdf9f87 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +@@ -78,6 +78,8 @@ + #define MAX_DWB_PIPES 1 + #define MAX_HPO_DP2_ENCODERS 4 + #define MAX_HPO_DP2_LINK_ENCODERS 4 ++#define MAX_HPO_HDMI_ENCODERS 1 ++#define MAX_HPO_HDMI_LINK_ENCODERS 1 + + /* Pipe topology snapshot structures */ + #define MAX_TOPOLOGY_SNAPSHOTS 4 +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +index d795fc43dc9d..aad69c708829 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +@@ -67,6 +67,7 @@ struct encoder_feature_support { + uint32_t IS_UHBR13_5_CAPABLE:1; + uint32_t IS_UHBR20_CAPABLE:1; + uint32_t DP_IS_USB_C:1; ++ uint32_t IS_HDMI_FRL_CAPABLE:1; + } bits; + uint32_t raw; + } flags; +@@ -239,6 +240,13 @@ struct hpo_dp_link_enc_state { + uint32_t vc_rate_y[4]; + }; + ++struct hpo_hdmi_link_enc_state { ++ uint32_t link_enc_enabled; ++ uint32_t lane_count; ++ uint32_t training_enabled; ++ uint32_t scrambler_disabled; ++}; ++ + struct hpo_dp_link_encoder { + const struct hpo_dp_link_encoder_funcs *funcs; + struct dc_context *ctx; +@@ -248,6 +256,15 @@ struct hpo_dp_link_encoder { + enum hpd_source_id hpd_source; + }; + ++struct hpo_hdmi_link_encoder { ++ const struct hpo_hdmi_link_encoder_funcs *funcs; ++ struct dc_context *ctx; ++ int inst; ++ enum engine_id preferred_engine; ++ enum transmitter transmitter; ++ enum hpd_source_id hpd_source; ++}; ++ + struct hpo_dp_link_encoder_funcs { + + void (*enable_link_phy)(struct hpo_dp_link_encoder *enc, +@@ -291,4 +308,33 @@ struct hpo_dp_link_encoder_funcs { + uint8_t ffe_preset); + }; + ++struct hpo_hdmi_link_encoder_funcs { ++ ++ /* Enable / disable HDMI FRL link encoder */ ++ void (*link_enable)( ++ struct hpo_hdmi_link_encoder *enc, ++ uint8_t lane_count); ++ ++ void (*link_disable)( ++ struct hpo_hdmi_link_encoder *enc); ++ ++ void (*configure_transmitter)( ++ struct hpo_hdmi_link_encoder *enc, ++ const struct dc_link *link, ++ uint8_t frl_rate, ++ enum transmitter transmitter, ++ enum hpd_source_id hpd_source); ++ ++ void (*set_training_enable)( ++ struct hpo_hdmi_link_encoder *enc, ++ bool enable); ++ ++ void (*set_training_patterns)( ++ struct hpo_hdmi_link_encoder *enc, ++ uint8_t lane0_ltp, ++ uint8_t lane1_ltp, ++ uint8_t lane2_ltp, ++ uint8_t lane3_ltp); ++}; ++ + #endif /* LINK_ENCODER_H_ */ +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +index 27f950ae45ee..d45d7b024e75 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +@@ -288,6 +288,12 @@ struct hpo_dp_stream_encoder_state { + uint32_t mapped_to_link_enc; + }; + ++struct hpo_hdmi_stream_encoder_state { ++ uint32_t stream_enc_enabled; ++ uint32_t otg_inst; ++ uint32_t pixel_encoding; ++}; ++ + struct hpo_dp_stream_encoder { + const struct hpo_dp_stream_encoder_funcs *funcs; + struct dc_context *ctx; +@@ -298,6 +304,17 @@ struct hpo_dp_stream_encoder { + struct apg *apg; + }; + ++struct hpo_hdmi_stream_encoder { ++ const struct hpo_hdmi_stream_encoder_funcs *funcs; ++ struct dc_context *ctx; ++ struct dc_bios *bp; ++ uint32_t inst; ++ enum engine_id id; ++ ++ struct vpg *vpg; ++ struct afmt *afmt; ++}; ++ + struct hpo_dp_stream_encoder_funcs { + void (*enable_stream)( + struct hpo_dp_stream_encoder *enc); +@@ -362,4 +379,39 @@ struct hpo_dp_stream_encoder_funcs { + uint16_t width); + }; + ++struct hpo_hdmi_stream_encoder_funcs { ++ void (*enable)( ++ struct hpo_hdmi_stream_encoder *enc, ++ uint8_t source_select); ++ ++ void (*disable)( ++ struct hpo_hdmi_stream_encoder *enc); ++ ++ void (*setup_stream_attribute)( ++ struct hpo_hdmi_stream_encoder *enc, ++ struct dc_crtc_timing *crtc_timing, ++ enum dc_color_space output_color_space); ++ ++ void (*update_hdmi_info_packets)( ++ struct hpo_hdmi_stream_encoder *enc, ++ const struct encoder_info_frame *info_frame); ++ ++ void (*stop_hdmi_info_packets)( ++ struct hpo_hdmi_stream_encoder *enc); ++ ++ void (*hdmi_audio_setup)( ++ struct hpo_hdmi_stream_encoder *enc, ++ unsigned int az_inst, ++ struct audio_info *info, ++ struct audio_crtc_info *audio_crtc_info, ++ uint8_t frl_rate); ++ ++ void (*hdmi_audio_enable)( ++ struct hpo_hdmi_stream_encoder *enc); ++ ++ void (*hdmi_audio_disable)( ++ struct hpo_hdmi_stream_encoder *enc); ++}; ++ ++ + #endif /* STREAM_ENCODER_H_ */ +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +index da7bf59c4b9d..9cf729d341f4 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +@@ -106,6 +106,7 @@ enum crc_selection { + + enum otg_out_mux_dest { + OUT_MUX_DIO = 0, ++ OUT_MUX_HPO_HDMI = 1, + OUT_MUX_HPO_DP = 2, + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h +index 0f69946cce9f..f0224cd3bf44 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h +@@ -56,6 +56,10 @@ struct link_hwss_ext { + enum signal_type signal, + enum clock_source_id clock_source, + const struct dc_link_settings *link_settings); ++ void (*enable_hdmi_link_output)(struct dc_link *link, ++ const struct link_resource *link_res, ++ enum signal_type signal, ++ const struct dc_link_settings *link_settings); + void (*set_dp_link_test_pattern)(struct dc_link *link, + const struct link_resource *link_res, + struct encoder_set_dp_phy_pattern_param *tp_params); +diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h +index 79746d931471..05d4450562d4 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h +@@ -59,6 +59,8 @@ struct resource_caps { + unsigned int num_usb4_dpia; // Total number of USB4 DPIA (DisplayPort Input Adapters). + int num_hpo_dp_stream_encoder; + int num_hpo_dp_link_encoder; ++ int num_hpo_hdmi_stream_encoder; ++ int num_hpo_hdmi_link_encoder; + int num_mpc_3dlut; + }; + +@@ -90,6 +92,13 @@ struct resource_create_funcs { + struct hpo_dp_link_encoder *(*create_hpo_dp_link_encoder)( + uint8_t inst, + struct dc_context *ctx); ++ ++ struct hpo_hdmi_stream_encoder *(*create_hpo_hdmi_stream_encoder)( ++ enum engine_id eng_id, struct dc_context *ctx); ++ struct hpo_hdmi_link_encoder *(*create_hpo_hdmi_link_encoder)( ++ uint8_t inst, ++ struct dc_context *ctx); ++ + struct dce_hwseq *(*create_hwseq)( + struct dc_context *ctx); + }; +diff --git a/drivers/gpu/drm/amd/display/dc/link/Makefile b/drivers/gpu/drm/amd/display/dc/link/Makefile +index 84dace27daf7..b972cc3cadcd 100644 +--- a/drivers/gpu/drm/amd/display/dc/link/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/link/Makefile +@@ -43,7 +43,8 @@ AMD_DISPLAY_FILES += $(AMD_DAL_LINK_ACCESSORIES) + # hwss + ############################################################################### + LINK_HWSS = link_hwss_dio.o link_hwss_dpia.o link_hwss_hpo_dp.o \ +-link_hwss_dio_fixed_vs_pe_retimer.o link_hwss_hpo_fixed_vs_pe_retimer_dp.o ++link_hwss_dio_fixed_vs_pe_retimer.o link_hwss_hpo_fixed_vs_pe_retimer_dp.o \ ++link_hwss_hpo_frl.o + + AMD_DAL_LINK_HWSS = $(addprefix $(AMDDALPATH)/dc/link/hwss/, \ + $(LINK_HWSS)) +@@ -56,7 +57,9 @@ LINK_PROTOCOLS = link_hpd.o link_ddc.o link_dpcd.o link_dp_dpia.o \ + link_dp_training.o link_dp_training_8b_10b.o link_dp_training_128b_132b.o \ + link_dp_training_dpia.o link_dp_training_auxless.o \ + link_dp_training_fixed_vs_pe_retimer.o link_dp_phy.o link_dp_capability.o \ +-link_edp_panel_control.o link_dp_panel_replay.o link_dp_irq_handler.o link_dp_dpia_bw.o ++link_edp_panel_control.o link_dp_panel_replay.o link_dp_irq_handler.o \ ++link_dp_dpia_bw.o link_frl_training.o ++ + + AMD_DAL_LINK_PROTOCOLS = $(addprefix $(AMDDALPATH)/dc/link/protocols/, \ + $(LINK_PROTOCOLS)) +diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c +new file mode 100644 +index 000000000000..c3e66e66e43e +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c +@@ -0,0 +1,132 @@ ++/* ++ * HPO HDMI link sequencing ++ * ++ * Copyright 2026 Michał Kopeć ++ */ ++ ++#include "link_hwss_hpo_frl.h" ++#include "core_types.h" ++#include "dccg.h" ++#include "dm_helpers.h" ++ ++#define DC_LOGGER link->ctx->logger ++ ++bool can_use_hpo_hdmi_frl_link_hwss(const struct dc_link *link, ++ const struct link_resource *link_res) ++{ ++ return link_res->hpo_hdmi_link_enc != NULL; ++} ++ ++static void enable_hpo_hdmi_frl_link_output( ++ struct dc_link *link, const struct link_resource *link_res, ++ enum signal_type signal, const struct dc_link_settings *link_settings) ++{ ++ struct hpo_hdmi_link_encoder *enc; ++ uint8_t frl_rate; ++ uint8_t lane_count; ++ ++ enc = link_res->hpo_hdmi_link_enc; ++ frl_rate = link_settings->frl_rate; ++ lane_count = (frl_rate <= 2) ? 3 : 4; ++ ++ enc->funcs->configure_transmitter(enc, link, frl_rate, ++ link->link_enc->transmitter, ++ link->link_enc->hpd_source); ++ ++ enc->funcs->link_enable(enc, lane_count); ++} ++ ++static void ++disable_hpo_hdmi_frl_link_output(struct dc_link *link, ++ const struct link_resource *link_res, ++ enum signal_type signal) ++{ ++ struct hpo_hdmi_link_encoder *enc; ++ ++ if (!link_res->hpo_hdmi_link_enc) ++ return; ++ ++ enc = link_res->hpo_hdmi_link_enc; ++ ++ enc->funcs->link_disable(enc); ++} ++ ++static void setup_hpo_hdmi_frl_stream_encoder(struct pipe_ctx *pipe_ctx) ++{ ++ struct hpo_hdmi_stream_encoder *stream_enc = ++ pipe_ctx->stream_res.hpo_hdmi_stream_enc; ++ ++ uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; ++ stream_enc->funcs->enable(stream_enc, otg_inst); ++} ++ ++static void reset_hpo_hdmi_frl_stream_encoder(struct pipe_ctx *pipe_ctx) ++{ ++ struct hpo_hdmi_stream_encoder *stream_enc = ++ pipe_ctx->stream_res.hpo_hdmi_stream_enc; ++ ++ if (!stream_enc) ++ return; ++ ++ stream_enc->funcs->stop_hdmi_info_packets(stream_enc); ++ stream_enc->funcs->disable(stream_enc); ++} ++ ++static void setup_hpo_hdmi_frl_stream_attribute(struct pipe_ctx *pipe_ctx) ++{ ++ struct hpo_hdmi_stream_encoder *stream_enc = ++ pipe_ctx->stream_res.hpo_hdmi_stream_enc; ++ struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; ++ enum dc_color_space output_color_space = ++ pipe_ctx->stream->output_color_space; ++ ++ if (!stream_enc) ++ return; ++ ++ stream_enc->funcs->setup_stream_attribute(stream_enc, timing, ++ output_color_space); ++} ++ ++static void setup_hpo_hdmi_frl_audio_output(struct pipe_ctx *pipe_ctx, ++ struct audio_output *audio_output, ++ uint32_t audio_inst) ++{ ++ pipe_ctx->stream_res.hpo_hdmi_stream_enc->funcs->hdmi_audio_setup( ++ pipe_ctx->stream_res.hpo_hdmi_stream_enc, audio_inst, ++ &pipe_ctx->stream->audio_info, &audio_output->crtc_info, ++ pipe_ctx->link_config.dp_link_settings.frl_rate); ++} ++ ++static void enable_hpo_hdmi_frl_audio_packet(struct pipe_ctx *pipe_ctx) ++{ ++ pipe_ctx->stream_res.hpo_hdmi_stream_enc->funcs->hdmi_audio_enable( ++ pipe_ctx->stream_res.hpo_hdmi_stream_enc); ++} ++ ++static void disable_hpo_hdmi_frl_audio_packet(struct pipe_ctx *pipe_ctx) ++{ ++ if (pipe_ctx->stream_res.audio) ++ pipe_ctx->stream_res.hpo_hdmi_stream_enc->funcs ++ ->hdmi_audio_disable( ++ pipe_ctx->stream_res.hpo_hdmi_stream_enc); ++} ++ ++static const struct link_hwss hpo_hdmi_frl_link_hwss = { ++ .setup_stream_encoder = setup_hpo_hdmi_frl_stream_encoder, ++ .reset_stream_encoder = reset_hpo_hdmi_frl_stream_encoder, ++ .setup_stream_attribute = setup_hpo_hdmi_frl_stream_attribute, ++ ++ .setup_audio_output = setup_hpo_hdmi_frl_audio_output, ++ .enable_audio_packet = enable_hpo_hdmi_frl_audio_packet, ++ .disable_audio_packet = disable_hpo_hdmi_frl_audio_packet, ++ ++ .disable_link_output = disable_hpo_hdmi_frl_link_output, ++ .ext = { ++ .enable_hdmi_link_output = enable_hpo_hdmi_frl_link_output, ++ }, ++}; ++ ++const struct link_hwss *get_hpo_hdmi_frl_link_hwss(void) ++{ ++ return &hpo_hdmi_frl_link_hwss; ++} +diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.h b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.h +new file mode 100644 +index 000000000000..6e6291b1e3c7 +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.h +@@ -0,0 +1,29 @@ ++/* ++ * HPO HDMI link sequencing ++ * ++ * Copyright 2026 Michał Kopeć ++ */ ++ ++#ifndef __LINK_HWSS_HPO_HDMI_FRL_H__ ++#define __LINK_HWSS_HPO_HDMI_FRL_H__ ++ ++#include "link_hwss.h" ++#include "link_service.h" ++ ++/* ++ * Returns true if the HPO HDMI FRL HWSS can be used for this link. ++ * ++ * Conditions: ++ * - HDMI signal ++ * - HPO HDMI link encoder present ++ * - FRL rate negotiated (frl_rate != 0) ++ */ ++bool can_use_hpo_hdmi_frl_link_hwss(const struct dc_link *link, ++ const struct link_resource *link_res); ++ ++/* ++ * Returns the HPO HDMI FRL link_hwss implementation. ++ */ ++const struct link_hwss *get_hpo_hdmi_frl_link_hwss(void); ++ ++#endif /* __LINK_HWSS_HPO_HDMI_FRL_H__ */ +diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c +index 578509e8d0e2..4021f53984ac 100644 +--- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c ++++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c +@@ -78,6 +78,7 @@ static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_ + case SIGNAL_TYPE_DVI_SINGLE_LINK: + case SIGNAL_TYPE_DVI_DUAL_LINK: + case SIGNAL_TYPE_HDMI_TYPE_A: ++ case SIGNAL_TYPE_HDMI_FRL: + case SIGNAL_TYPE_LVDS: + case SIGNAL_TYPE_RGB: + transaction_type = DDC_TRANSACTION_TYPE_I2C; +@@ -1019,10 +1020,11 @@ static bool detect_link_and_local_sink(struct dc_link *link, + + /* From Disconnected-to-Connected. */ + switch (link->connector_signal) { ++ case SIGNAL_TYPE_HDMI_FRL: + case SIGNAL_TYPE_HDMI_TYPE_A: { + sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; + if (aud_support->hdmi_audio_native) +- sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; ++ sink_caps.signal = link->connector_signal; + else + sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; + break; +@@ -1502,6 +1504,7 @@ bool link_is_hdcp14(struct dc_link *link, enum signal_type signal) + case SIGNAL_TYPE_DVI_SINGLE_LINK: + case SIGNAL_TYPE_DVI_DUAL_LINK: + case SIGNAL_TYPE_HDMI_TYPE_A: ++ case SIGNAL_TYPE_HDMI_FRL: + /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable, + * we can poll for bksv but some displays have an issue with this. Since its so rare + * for a display to not be 1.4 capable, this assumtion is ok +@@ -1528,6 +1531,7 @@ bool link_is_hdcp22(struct dc_link *link, enum signal_type signal) + case SIGNAL_TYPE_DVI_SINGLE_LINK: + case SIGNAL_TYPE_DVI_DUAL_LINK: + case SIGNAL_TYPE_HDMI_TYPE_A: ++ case SIGNAL_TYPE_HDMI_FRL: + ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0; + break; + default: +diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +index 91742bde4dc2..d0adcbe5cee5 100644 +--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c ++++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +@@ -48,6 +48,7 @@ + #include "protocols/link_edp_panel_control.h" + #include "protocols/link_dp_panel_replay.h" + #include "protocols/link_dp_dpia_bw.h" ++#include "protocols/link_frl_training.h" + + #include "dm_helpers.h" + #include "link_enc_cfg.h" +@@ -687,6 +688,9 @@ static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) + if (dp_is_128b_132b_signal(pipe_ctx)) + config.stream_enc_idx = + pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; ++ if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) ++ config.stream_enc_idx = ++ pipe_ctx->stream_res.hpo_hdmi_stream_enc->id - ENGINE_ID_HPO_0; + + /* dig back end */ + config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; +@@ -695,6 +699,8 @@ static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) + config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; + if (dp_is_128b_132b_signal(pipe_ctx)) + config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; ++ if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) ++ config.link_enc_idx = pipe_ctx->link_res.hpo_hdmi_link_enc->inst; + + /* dio output index is dpia index for DPIA endpoint & dcio index by default */ + if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) +@@ -1904,7 +1910,7 @@ static void disable_link(struct dc_link *link, + } + } + +-static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) ++static enum dc_status enable_link_hdmi(struct pipe_ctx *pipe_ctx) + { + struct dc_stream_state *stream = pipe_ctx->stream; + struct dc_link *link = stream->link; +@@ -1915,15 +1921,39 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) + bool is_vga_mode = (stream->timing.h_addressable == 640) + && (stream->timing.v_addressable == 480); + struct dc *dc = pipe_ctx->stream->ctx->dc; ++ ++ DC_LOG_HW_LINK_TRAINING("enable_link_hdmi entered\n"); ++ + const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); + ++ if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal) && ++ link_hwss->ext.enable_hdmi_link_output) { ++ ++ link->cur_link_settings.frl_rate = ++ pipe_ctx->link_config.dp_link_settings.frl_rate; ++ link->cur_link_settings.lane_count = ++ pipe_ctx->link_config.dp_link_settings.lane_count; ++ ++ link_hwss->ext.enable_hdmi_link_output( ++ link, ++ &pipe_ctx->link_res, ++ pipe_ctx->stream->signal, ++ &link->cur_link_settings); ++ ++ if (!dc_link_perform_frl_training(link, &pipe_ctx->link_res)) { ++ DC_LOG_HW_LINK_TRAINING("HDMI FRL: training failed\n"); ++ return DC_ERROR_UNEXPECTED; ++ } ++ return DC_OK; ++ } ++ + if (stream->phy_pix_clk == 0) + stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; + if (stream->phy_pix_clk > 340000) + is_over_340mhz = true; + if (dc_is_tmds_signal(stream->signal) && stream->phy_pix_clk > 6000000UL) { + ASSERT(false); +- return; ++ return DC_OK; + } + + if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { +@@ -1946,7 +1976,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) + } + } + +- if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) ++ if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) + write_scdc_data( + stream->link->ddc, + stream->phy_pix_clk, +@@ -1975,6 +2005,8 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) + + if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) + read_scdc_data(link->ddc); ++ ++ return DC_OK; + } + + static enum dc_status enable_link_dp(struct dc_state *state, +@@ -2179,6 +2211,7 @@ static enum dc_status enable_link( + return DC_ERROR_UNEXPECTED; + link = stream->link; + ++ DC_LOG_HW_LINK_TRAINING("enable_link entered\n"); + /* There's some scenarios where driver is unloaded with display + * still enabled. When driver is reloaded, it may cause a display + * to not light up if there is a mismatch between old and new +@@ -2187,6 +2220,7 @@ static enum dc_status enable_link( + */ + if (link->link_status.link_active) + disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); ++ DC_LOG_HW_LINK_TRAINING("link disabled\n"); + + switch (pipe_ctx->stream->signal) { + case SIGNAL_TYPE_DISPLAY_PORT: +@@ -2202,8 +2236,8 @@ static enum dc_status enable_link( + case SIGNAL_TYPE_DVI_SINGLE_LINK: + case SIGNAL_TYPE_DVI_DUAL_LINK: + case SIGNAL_TYPE_HDMI_TYPE_A: +- enable_link_hdmi(pipe_ctx); +- status = DC_OK; ++ case SIGNAL_TYPE_HDMI_FRL: ++ status = enable_link_hdmi(pipe_ctx); + break; + case SIGNAL_TYPE_LVDS: + enable_link_lvds(pipe_ctx); +@@ -2308,6 +2342,8 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx) + + if (dp_is_128b_132b_signal(pipe_ctx)) + vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; ++ else if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) ++ vpg = pipe_ctx->stream_res.hpo_hdmi_stream_enc->vpg; + if (dc_is_virtual_signal(pipe_ctx->stream->signal)) + return; + +@@ -2339,7 +2375,7 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx) + dp_is_128b_132b_signal(pipe_ctx)) + update_sst_payload(pipe_ctx, false); + +- if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { ++ if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) { + struct ext_hdmi_settings settings = {0}; + enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; + +@@ -2364,6 +2400,9 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx) + } + } + ++ if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) ++ dc_link_disable_frl(pipe_ctx->stream->link); ++ + if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && + !dp_is_128b_132b_signal(pipe_ctx)) { + +@@ -2386,7 +2425,7 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx) + if (dc_is_dp_signal(pipe_ctx->stream->signal)) + link_set_dsc_enable(pipe_ctx, false); + } +- if (dp_is_128b_132b_signal(pipe_ctx)) { ++ if (dp_is_128b_132b_signal(pipe_ctx) || dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) { + if (pipe_ctx->stream_res.tg->funcs->set_out_mux) + pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); + } +@@ -2424,6 +2463,8 @@ void link_set_dpms_on( + + if (dp_is_128b_132b_signal(pipe_ctx)) + vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; ++ else if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) ++ vpg = pipe_ctx->stream_res.hpo_hdmi_stream_enc->vpg; + if (dc_is_virtual_signal(pipe_ctx->stream->signal)) + return; + +@@ -2443,7 +2484,8 @@ void link_set_dpms_on( + ASSERT(link_enc); + + if (!dc_is_virtual_signal(pipe_ctx->stream->signal) +- && !dp_is_128b_132b_signal(pipe_ctx)) { ++ && !dp_is_128b_132b_signal(pipe_ctx) ++ && !dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) { + if (link_enc) + link_enc->funcs->setup( + link_enc, +@@ -2455,6 +2497,10 @@ void link_set_dpms_on( + if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { + if (dp_is_128b_132b_signal(pipe_ctx)) + otg_out_dest = OUT_MUX_HPO_DP; ++ else if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) ++ /* DCN401 unified the DP and HDMI output mux values */ ++ otg_out_dest = (dc->ctx->dce_version < DCN_VERSION_4_01) ? ++ OUT_MUX_HPO_HDMI : OUT_MUX_HPO_DP; + else + otg_out_dest = OUT_MUX_DIO; + pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); +@@ -2566,7 +2612,8 @@ void link_set_dpms_on( + * from transmitter control. + */ + if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || +- dp_is_128b_132b_signal(pipe_ctx))) { ++ dp_is_128b_132b_signal(pipe_ctx) || ++ dc_is_hdmi_frl_signal(pipe_ctx->stream->signal))) { + + if (link_enc) + link_enc->funcs->setup( +diff --git a/drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_frl.c b/drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_frl.c +deleted file mode 100644 +index 4b5eccd994c4..000000000000 +--- a/drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_frl.c ++++ /dev/null +@@ -1,62 +0,0 @@ +-/* +- * Copyright 2022 Advanced Micro Devices, Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: AMD +- * +- */ +-#include "link_hwss_hpo_frl.h" +-#include "core_types.h" +-#include "virtual/virtual_link_hwss.h" +- +-static void setup_hpo_frl_stream_attribute(struct pipe_ctx *pipe_ctx) +-{ +- struct hpo_frl_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_frl_stream_enc; +- struct dc_stream_state *stream = pipe_ctx->stream; +- struct pipe_ctx *odm_pipe; +- int odm_combine_num_segments = 1; +- +- /* get number of ODM combine input segments */ +- for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) +- odm_combine_num_segments++; +- +- stream_enc->funcs->hdmi_frl_set_stream_attribute( +- stream_enc, +- &stream->timing, +- &stream->link->frl_link_settings.borrow_params, +- odm_combine_num_segments); +-} +- +-static const struct link_hwss hpo_frl_link_hwss = { +- .setup_stream_encoder = virtual_setup_stream_encoder, +- .reset_stream_encoder = virtual_reset_stream_encoder, +- .setup_stream_attribute = setup_hpo_frl_stream_attribute, +-}; +- +-bool can_use_hpo_frl_link_hwss(const struct dc_link *link, +- const struct link_resource *link_res) +-{ +- return link_res->hpo_frl_link_enc != NULL; +-} +- +-const struct link_hwss *get_hpo_frl_link_hwss(void) +-{ +- return &hpo_frl_link_hwss; +-} +diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c +index 5d2bcce2f669..6c5ee009fa6d 100644 +--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c ++++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c +@@ -596,7 +596,7 @@ void read_scdc_data(struct ddc_service *ddc_service) + link_query_ddc_data(ddc_service, slave_address, + &offset, sizeof(offset), &scramble_status, + sizeof(scramble_status)); +- offset = HDMI_SCDC_STATUS_FLAGS; ++ offset = HDMI_SCDC_STATUS_FLAGS_0; + link_query_ddc_data(ddc_service, slave_address, + &offset, sizeof(offset), &status_data.byte, + sizeof(status_data.byte)); +diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_frl_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_frl_training.c +new file mode 100644 +index 000000000000..5e83c2bb4256 +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_frl_training.c +@@ -0,0 +1,581 @@ ++/* ++ * HDMI 2.1 Fixed Rate Link (FRL) training ++ * ++ * Copyright 2026 Michał Kopeć ++ */ ++ ++#include "link_frl_training.h" ++#include "core_types.h" ++#include "dm_helpers.h" ++#include "link_hwss.h" ++#include "link_ddc.h" ++#include "dc_hdmi_types.h" ++ ++#define DC_LOGGER link->ctx->logger ++ ++#define SCDC_FLT_READY_BIT 0x40 ++#define SCDC_FLT_UPDATE_BIT 0x20 ++#define SCDC_FRL_START_BIT 0x10 ++ ++#define HDMI_LTP_PASS 0x0 ++#define HDMI_LTP_NEXT_FFE 0xE ++#define HDMI_LTP_LOWER_RATE 0xF ++ ++#define FRL_MAX_LANES 4 ++#define FRL_POLL_DELAY_MS 2 ++#define FRL_MAX_POLLS 100 ++ ++static bool frl_read_scdc(struct dc_link *link, uint8_t offset, void *buf, ++ uint32_t size) ++{ ++ uint8_t slave_address = HDMI_SCDC_ADDRESS; ++ ++ return link_query_ddc_data(link->ddc, slave_address, &offset, ++ sizeof(offset), buf, size); ++} ++ ++static bool frl_write_scdc(struct dc_link *link, uint8_t offset, ++ const void *buf, uint32_t size) ++{ ++ uint8_t slave_address = HDMI_SCDC_ADDRESS; ++ uint8_t write_buffer[17] = { 0 }; ++ ++ if (size > 16) ++ return false; ++ ++ write_buffer[0] = offset; ++ for (int i = 0; i < size; ++i) ++ write_buffer[i + 1] = ((uint8_t *)buf)[i]; ++ ++ return link_query_ddc_data(link->ddc, slave_address, write_buffer, ++ size + 1, NULL, 0); ++} ++ ++bool dc_link_perform_frl_training(struct dc_link *link, ++ const struct link_resource *link_res) ++{ ++ struct hpo_hdmi_link_encoder *enc = link_res->hpo_hdmi_link_enc; ++ uint8_t lane_count = link->cur_link_settings.lane_count; ++ uint8_t frl_rate = link->cur_link_settings.frl_rate; ++ uint8_t sink_version; ++ uint8_t update; ++ uint8_t status; ++ uint16_t ltp_req; ++ uint8_t write_buffer[2]; ++ int poll; ++ int lane; ++ int post_training_timeout; ++ ++ if (!enc || lane_count == 0 || lane_count > FRL_MAX_LANES) ++ return false; ++ ++ DC_LOG_HW_LINK_TRAINING( ++ "HDMI FRL: starting training (rate=%u lanes=%u)\n", frl_rate, ++ lane_count); ++ ++ /* ------------------------------------------------------------------ */ ++ /* Step 1: Read sink version */ ++ /* ------------------------------------------------------------------ */ ++ if (!frl_read_scdc(link, HDMI_SCDC_SINK_VERSION, &sink_version, 1)) { ++ DC_LOG_ERROR("FRL: failed to read sink version\n"); ++ return false; ++ } ++ ++ if (sink_version == 0) { ++ DC_LOG_HW_LINK_TRAINING("FRL: sink does not support FRL\n"); ++ return false; ++ } ++ ++ /* Write source version = 1 */ ++ write_buffer[0] = 0x01; ++ frl_write_scdc(link, HDMI_SCDC_SOURCE_VERSION, write_buffer, 1); ++ ++retrain: ++ /* Reset FRL rate */ ++ write_buffer[0] = 0; ++ write_buffer[1] = 0; ++ frl_write_scdc(link, HDMI_SCDC_CONFIG_0, write_buffer, 2); ++ ++ /* ------------------------------------------------------------------ */ ++ /* Step 2: Wait for FLT_READY */ ++ /* ------------------------------------------------------------------ */ ++ for (poll = 0; poll < FRL_MAX_POLLS; poll++) { ++ if (!frl_read_scdc(link, HDMI_SCDC_STATUS_FLAGS_0, &status, 1)) { ++ msleep(FRL_POLL_DELAY_MS); ++ continue; ++ } ++ ++ if (status & SCDC_FLT_READY_BIT) ++ break; ++ ++ msleep(FRL_POLL_DELAY_MS); ++ } ++ ++ if (!(status & SCDC_FLT_READY_BIT)) { ++ DC_LOG_ERROR("FRL: FLT_READY timeout\n"); ++ return false; ++ } ++ ++ /* Write FRL rate */ ++ write_buffer[0] = 0; ++ write_buffer[1] = frl_rate; ++ frl_write_scdc(link, HDMI_SCDC_CONFIG_0, write_buffer, 2); ++ ++ /* ------------------------------------------------------------------ */ ++ /* Step 3: Enable FRL training in HW */ ++ /* ------------------------------------------------------------------ */ ++ enc->funcs->set_training_enable(enc, true); ++ ++ pr_err("FRL DEBUG: entering training loop\n"); ++ ++ for (poll = 0; poll < FRL_MAX_POLLS; poll++) { ++ pr_err("FRL DEBUG: poll %d\n", poll); ++ ++ /* Read UPDATE_0 */ ++ if (!frl_read_scdc(link, HDMI_SCDC_UPDATE_0, &update, 1)) { ++ pr_err("FRL DEBUG: failed to read SCDC_UPDATE_0\n"); ++ msleep(FRL_POLL_DELAY_MS); ++ continue; ++ } ++ ++ pr_err("FRL DEBUG: UPDATE_0 = 0x%02x\n", update); ++ ++ if (!(update & SCDC_FLT_UPDATE_BIT)) { ++ pr_err("FRL DEBUG: FLT_UPDATE not set\n"); ++ msleep(FRL_POLL_DELAY_MS); ++ continue; ++ } ++ ++ pr_err("FRL DEBUG: FLT_UPDATE asserted\n"); ++ ++ /* Clear UPDATE_0 */ ++ if (!frl_write_scdc(link, HDMI_SCDC_UPDATE_0, &update, 1)) { ++ pr_err("FRL DEBUG: failed to clear SCDC_UPDATE_0\n"); ++ msleep(FRL_POLL_DELAY_MS); ++ continue; ++ } ++ ++ /* Read STATUS_FLAGS_1 (LTP requests) */ ++ if (!frl_read_scdc(link, HDMI_SCDC_STATUS_FLAGS_1, <p_req, 2)) { ++ pr_err("FRL DEBUG: failed to read SCDC_STATUS_FLAGS_1\n"); ++ continue; ++ } ++ ++ /* Decode per-lane LTP */ ++ for (lane = 0; lane < lane_count; lane++) { ++ uint8_t ltp = (ltp_req >> (lane * 4)) & 0xF; ++ pr_err("FRL DEBUG: lane %d LTP = 0x%x\n", lane, ltp); ++ } ++ ++ /* Check for PASS on all active lanes */ ++ for (lane = 0; lane < lane_count; lane++) { ++ uint8_t ltp = (ltp_req >> (lane * 4)) & 0xF; ++ if (ltp != HDMI_LTP_PASS) ++ break; ++ } ++ ++ if (lane == lane_count) { ++ enc->funcs->set_training_enable(enc, false); ++ for (post_training_timeout = 0; ++ post_training_timeout < FRL_MAX_POLLS; ++ post_training_timeout++) { ++ if (!frl_read_scdc(link, HDMI_SCDC_UPDATE_0, &update, 1)) { ++ msleep(FRL_POLL_DELAY_MS); ++ continue; ++ } ++ ++ if (update & (SCDC_FLT_UPDATE_BIT | SCDC_FRL_START_BIT)) ++ break; ++ ++ msleep(FRL_POLL_DELAY_MS); ++ } ++ ++ frl_write_scdc(link, HDMI_SCDC_UPDATE_0, &update, 1); ++ ++ if (update & SCDC_FRL_START_BIT) { ++ DC_LOG_HW_LINK_TRAINING("HDMI FRL: training successful\n"); ++ return true; ++ } else if (update & SCDC_FLT_UPDATE_BIT) { ++ DC_LOG_HW_LINK_TRAINING("HDMI FRL: retraining needed\n"); ++ goto retrain; ++ } else { ++ DC_LOG_HW_LINK_TRAINING("HDMI FRL: did not receive status update!\n"); ++ return false; ++ } ++ } ++ ++ /* Program requested training patterns */ ++ pr_err("FRL DEBUG: programming training patterns\n"); ++ enc->funcs->set_training_patterns(enc, ++ ((ltp_req >> 0) & 0xF) - 1, ++ ((ltp_req >> 4) & 0xF) - 1, ++ ((ltp_req >> 8) & 0xF) - 1, ++ ((ltp_req >> 12) & 0xF) - 1); ++ ++ /* Detect LOWER_RATE / NEXT_FFE */ ++ for (lane = 0; lane < lane_count; lane++) { ++ uint8_t ltp = (ltp_req >> (lane * 4)) & 0xF; ++ ++ if (ltp == HDMI_LTP_LOWER_RATE) { ++ pr_err("FRL DEBUG: lane %d requested LOWER_RATE\n", ++ lane); ++ DC_LOG_ERROR( ++ "FRL: sink requested lower rate (unsupported)\n"); ++ goto fail; ++ } ++ ++ if (ltp == HDMI_LTP_NEXT_FFE) { ++ pr_err("FRL DEBUG: lane %d requested NEXT_FFE (ignored)\n", ++ lane); ++ } ++ } ++ ++ msleep(FRL_POLL_DELAY_MS); ++ } ++ ++fail: ++ DC_LOG_ERROR("FRL: training failed\n"); ++ ++ /* Reset FRL rate */ ++ write_buffer[0] = 0; ++ write_buffer[1] = 0; ++ frl_write_scdc(link, 0x30, write_buffer, 2); ++ ++ return false; ++} ++ ++void dc_link_disable_frl(struct dc_link *link) ++{ ++ uint8_t write_buffer[2]; ++ ++ /* Inform the sink not to expect an FRL signal */ ++ write_buffer[0] = 0; ++ write_buffer[1] = 0; ++ frl_write_scdc(link, HDMI_SCDC_CONFIG_0, write_buffer, 2); ++} ++ ++/* DFM calc ++ * References: ++ * https://github.com/openharmony/device_soc_hisilicon/blob/master/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/drv_hdmi_dfm.c#L264 ++ * https://github.com/jelyoussefi/intel-gpu-i915/blob/e366083d562341ce15d5fe1a39bb6e07f18a4745/drivers/gpu/drm/i915/display/intel_hdmi.c#L4217 ++ * TODO Move to generic DRM */ ++ ++#define DFM_TOLERANCE_PIXEL_CLOCK_PCT_X1000 5 /* +0.50% -> 5/1000 */ ++#define DFM_TOLERANCE_AUDIO_CLOCK_PPM 1000 /* +/- 1000 ppm */ ++#define DFM_TOLERANCE_FRL_BIT_RATE_PPM 300 /* +/- 300 ppm */ ++#define DFM_TB_BORROWED_MAX 400 ++#define DFM_FRL_CFRL_CB 510 ++ ++struct dfm_config { ++ /* Video Timing */ ++ uint32_t pixel_clock_khz; /* Nominal */ ++ uint32_t hactive; ++ uint32_t hblank; ++ uint32_t bpc; /* Bits per component */ ++ enum dc_pixel_encoding encoding; ++ ++ /* FRL Configuration */ ++ uint32_t frl_bit_rate_gbps; /* 3, 6, 8, 10, 12 */ ++ uint8_t lanes; /* 3 or 4 */ ++ ++ /* Audio */ ++ bool audio_enable; ++ uint32_t audio_freq_hz; ++ uint8_t audio_channels; ++}; ++ ++struct dfm_results { ++ /* Calculated Parameters */ ++ uint64_t f_pixel_clock_max; ++ uint64_t r_frl_char_min; ++ uint32_t overhead_ppm; ++ ++ /* Audio */ ++ uint32_t audio_packets_line; ++ uint32_t hblank_audio_min; ++ ++ /* Tri-Bytes */ ++ uint32_t tb_active; ++ uint32_t tb_blank; ++ ++ /* Compression */ ++ uint32_t cfrl_rc_savings; ++ ++ /* Timing (ns) */ ++ uint64_t t_active_min; ++ uint64_t t_active_ref; ++ uint64_t t_blank_min; ++ uint64_t t_blank_ref; ++ ++ /* Borrowing */ ++ uint64_t tb_borrowed; ++ ++ /* Utilization */ ++ uint32_t cfrl_line; ++ uint32_t cfrl_actual_payload; ++ int32_t margin_ppm; /* Can be negative */ ++ ++ /* Pass/Fail Flags */ ++ bool audio_supported; ++ bool dfm_supported; ++ bool utilization_supported; ++ bool total_supported; ++}; ++ ++ ++#define CEILING(x, y) (((x) + (y) - 1) / (y)) ++ ++static uint32_t calc_overhead_ppm(uint8_t lanes) ++{ ++ uint32_t cfrl_sb = (4 * 510) + lanes; ++ ++ uint64_t oh_sb_num = (uint64_t)lanes * 1000000ULL; ++ uint32_t oh_sb = (uint32_t)((oh_sb_num + (cfrl_sb/2)) / cfrl_sb); /* Rounding */ ++ ++ uint64_t oh_rs_num = 32ULL * 1000000ULL; ++ uint32_t oh_rs = (uint32_t)((oh_rs_num + (cfrl_sb/2)) / cfrl_sb); ++ ++ uint64_t oh_map_num = 2500000ULL; /* 2.5 * 1M */ ++ uint32_t oh_map = (uint32_t)((oh_map_num + (cfrl_sb/2)) / cfrl_sb); ++ ++ uint32_t oh_m = 3000; ++ ++ return oh_sb + oh_rs + oh_map + oh_m; ++} ++ ++static void calc_audio(const struct dfm_config *cfg, ++ uint64_t t_line_ns, ++ struct dfm_results *res) ++{ ++ if (!cfg->audio_enable) { ++ res->audio_packets_line = 0; ++ res->hblank_audio_min = 64; ++ return; ++ } ++ ++ uint32_t ap = 1; ++ if (cfg->audio_channels > 22) { ++ ap = 4; /* ACAT 3 (up to 30.2ch) */ ++ } else if (cfg->audio_channels > 10) { ++ ap = 3; /* ACAT 2 (up to 22.2ch) */ ++ } else if (cfg->audio_channels > 8) { ++ ap = 2; /* ACAT 1 (up to 10.2ch) */ ++ } else { ++ ap = 1; /* Layout 0/1 */ ++ } ++ ++ uint64_t rap = (uint64_t)cfg->audio_freq_hz * (1000000 + DFM_TOLERANCE_AUDIO_CLOCK_PPM); ++ rap = (rap * ap) / 1000000; ++ ++ uint64_t avg_pkts_x1000 = (rap * t_line_ns) / 1000000; /* ns to ms scale */ ++ ++ res->audio_packets_line = (uint32_t)((avg_pkts_x1000 + 999) / 1000); ++ ++ res->hblank_audio_min = 64 + (32 * res->audio_packets_line); ++} ++ ++/* Table 6-44: RC Compression Savings */ ++static void calc_rc_compression(const struct dfm_config *cfg, struct dfm_results *res) ++{ ++ uint32_t k420 = (cfg->encoding == PIXEL_ENCODING_YCBCR420) ? 2 : 1; ++ uint32_t kcd = (cfg->encoding == PIXEL_ENCODING_YCBCR422) ? 1 : cfg->bpc; ++ ++ uint64_t raw_num = (uint64_t)cfg->hblank * kcd * 8; ++ uint64_t raw_den = (uint64_t)k420 * 7; ++ uint32_t raw_capacity = (uint32_t)(raw_num / raw_den); /* FLOOR */ ++ ++ uint32_t deduct = 32 * (1 + res->audio_packets_line) + 7; ++ int32_t free_chars = (int32_t)raw_capacity - (int32_t)deduct; ++ ++ if (free_chars < 0) free_chars = 0; ++ ++ int32_t margin = 4; ++ ++ int32_t base = free_chars - margin; ++ if (base < 0) base = 0; ++ ++ res->cfrl_rc_savings = (uint32_t)((base * 7) / 8); ++} ++ ++/* Core DFM Check Function */ ++static void perform_dfm_check(const struct dfm_config *cfg, struct dfm_results *res) ++{ ++ memset(res, 0, sizeof(struct dfm_results)); ++ ++ uint32_t htotal = cfg->hactive + cfg->hblank; ++ ++ res->overhead_ppm = calc_overhead_ppm(cfg->lanes); ++ ++ res->f_pixel_clock_max = (uint64_t)cfg->pixel_clock_khz * 1000; ++ res->f_pixel_clock_max = res->f_pixel_clock_max * (1000 + DFM_TOLERANCE_PIXEL_CLOCK_PCT_X1000) / 1000; ++ ++ uint64_t t_line_ns = ((uint64_t)htotal * 1000000000ULL) / res->f_pixel_clock_max; ++ ++ uint64_t r_bit_nominal = (uint64_t)cfg->frl_bit_rate_gbps * 1000000000ULL; ++ uint64_t r_bit_min = r_bit_nominal * (1000000 - DFM_TOLERANCE_FRL_BIT_RATE_PPM) / 1000000; ++ ++ res->r_frl_char_min = r_bit_min / 18; ++ ++ uint64_t cap_calc = (t_line_ns * res->r_frl_char_min * cfg->lanes) / 1000000000ULL; ++ res->cfrl_line = (uint32_t)cap_calc; ++ ++ calc_audio(cfg, t_line_ns, res); ++ ++ calc_rc_compression(cfg, res); ++ ++ uint32_t bpp; ++ uint32_t k420 = (cfg->encoding == PIXEL_ENCODING_YCBCR420) ? 2 : 1; ++ uint32_t kcd = (cfg->encoding == PIXEL_ENCODING_YCBCR422) ? 1 : cfg->bpc; ++ ++ bpp = (24 * kcd) / (k420 * 8); ++ ++ uint64_t bytes_line = ((uint64_t)bpp * cfg->hactive) / 8; ++ ++ res->tb_active = (uint32_t)CEILING(bytes_line, 3); ++ ++ uint64_t tb_blank_num = (uint64_t)cfg->hblank * kcd; ++ uint64_t tb_blank_den = (uint64_t)k420 * 8; ++ res->tb_blank = (uint32_t)CEILING(tb_blank_num, tb_blank_den); ++ ++ if (res->hblank_audio_min <= res->tb_blank) { ++ res->audio_supported = true; ++ } else { ++ res->audio_supported = false; ++ res->total_supported = false; ++ return; ++ } ++ ++ uint64_t tb_total = res->tb_active + res->tb_blank; ++ uint64_t f_tb_avg = (res->f_pixel_clock_max * tb_total) / htotal; ++ ++ res->t_active_ref = (t_line_ns * cfg->hactive) / htotal; ++ ++ res->t_blank_ref = (t_line_ns * cfg->hblank) / htotal; ++ ++ uint64_t r_frl_eff = res->r_frl_char_min * (1000000 - res->overhead_ppm) / 1000000; ++ ++ res->t_active_min = (3ULL * res->tb_active * 1000000000ULL) / (2ULL * cfg->lanes * r_frl_eff); ++ ++ res->t_blank_min = (res->tb_blank * 1000000000ULL) / (cfg->lanes * r_frl_eff); ++ ++ if (res->t_active_ref >= res->t_active_min && res->t_blank_ref >= res->t_blank_min) { ++ res->tb_borrowed = 0; ++ res->dfm_supported = true; ++ } else if (res->t_active_ref < res->t_active_min) { ++ uint64_t borrow_time_ns = res->t_active_min - res->t_active_ref; ++ ++ res->tb_borrowed = CEILING(borrow_time_ns * f_tb_avg, 1000000000ULL); ++ ++ if (res->tb_borrowed <= DFM_TB_BORROWED_MAX) { ++ res->dfm_supported = true; ++ } else { ++ res->dfm_supported = false; ++ } ++ } else { ++ /* Blanking needs more time than available */ ++ res->dfm_supported = false; ++ } ++ ++ if (!res->dfm_supported) { ++ res->total_supported = false; ++ return; ++ } ++ ++ uint64_t total_chars_req = (3 * tb_total) / 2; ++ if (total_chars_req > res->cfrl_rc_savings) { ++ res->cfrl_actual_payload = (uint32_t)CEILING((total_chars_req - res->cfrl_rc_savings), 1); ++ } else { ++ res->cfrl_actual_payload = 0; ++ } ++ ++ uint64_t util_ppm = ((uint64_t)res->cfrl_actual_payload * 1000000ULL) / res->cfrl_line; ++ ++ int32_t margin_ppm = 1000000 - (int32_t)util_ppm + (int32_t)res->overhead_ppm; ++ res->margin_ppm = margin_ppm; ++ ++ if (margin_ppm >= 0) { ++ res->utilization_supported = true; ++ res->total_supported = true; ++ } else { ++ res->utilization_supported = false; ++ res->total_supported = false; ++ } ++} ++ ++bool hdmi_decide_link_settings( ++ struct dc_stream_state *stream, ++ struct pipe_ctx *pipe_ctx) ++{ ++ struct dfm_config cfg; ++ struct dfm_results res; ++ uint8_t frl_rate; ++ static const uint32_t frl_rates_gbps[] = {3, 6, 6, 8, 10, 12}; ++ uint8_t max_rate = stream->link->local_sink->edid_caps.frl_caps.max_rate; ++ uint8_t best_borrow_rate = 0; ++ uint8_t best_borrow_lanes = 0; ++ struct dfm_results best_borrow_res = {0}; ++ ++ if (max_rate == 0 || max_rate > 6) ++ return false; ++ ++ memset(&cfg, 0, sizeof(cfg)); ++ ++ cfg.pixel_clock_khz = stream->timing.pix_clk_100hz / 10; ++ cfg.hactive = stream->timing.h_addressable; ++ cfg.hblank = stream->timing.h_total - stream->timing.h_addressable; ++ cfg.encoding = stream->timing.pixel_encoding; ++ ++ switch (stream->timing.display_color_depth) { ++ case COLOR_DEPTH_888: cfg.bpc = 8; break; ++ case COLOR_DEPTH_101010: cfg.bpc = 10; break; ++ case COLOR_DEPTH_121212: cfg.bpc = 12; break; ++ case COLOR_DEPTH_161616: cfg.bpc = 16; break; ++ default: ++ cfg.bpc = 8; ++ break; ++ } ++ ++ if (stream->audio_info.mode_count) { ++ cfg.audio_enable = true; ++ /* If we assume the worst case (e.g. 192KHz 32 channel audio) we risk ++ * unfairly pruning low res modes with short Hblank periods. Instead, ++ * assume a standard surround sound mode that should allow all video ++ * modes to work. ++ */ ++ cfg.audio_freq_hz = 48000; ++ cfg.audio_channels = 8; ++ } ++ ++ for (frl_rate = 1; frl_rate <= max_rate; frl_rate++) { ++ cfg.frl_bit_rate_gbps = frl_rates_gbps[frl_rate - 1]; ++ cfg.lanes = (frl_rate <= 2) ? 3 : 4; ++ ++ perform_dfm_check(&cfg, &res); ++ ++ if (res.total_supported) { ++ if (res.tb_borrowed == 0) { ++ pipe_ctx->link_config.dp_link_settings.frl_rate = frl_rate; ++ pipe_ctx->link_config.dp_link_settings.lane_count = cfg.lanes; ++ ++ pr_info("HDMI FRL: Rate %d Supported. Borrowed: 0, Margin: %d ppm\n", ++ frl_rate, res.margin_ppm); ++ return true; ++ } else if (best_borrow_rate == 0) { ++ best_borrow_rate = frl_rate; ++ best_borrow_lanes = cfg.lanes; ++ best_borrow_res = res; ++ } ++ } ++ } ++ ++ if (best_borrow_rate > 0) { ++ pipe_ctx->link_config.dp_link_settings.frl_rate = best_borrow_rate; ++ pipe_ctx->link_config.dp_link_settings.lane_count = best_borrow_lanes; ++ ++ pr_info("HDMI FRL: Rate %d Supported (with borrowing). Borrowed: %llu, Margin: %d ppm\n", ++ best_borrow_rate, best_borrow_res.tb_borrowed, best_borrow_res.margin_ppm); ++ return true; ++ } ++ ++ return false; ++} +\ No newline at end of file +diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_frl_training.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_frl_training.h +new file mode 100644 +index 000000000000..b6f23e6d8394 +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_frl_training.h +@@ -0,0 +1,53 @@ ++/* ++ * HDMI 2.1 Fixed Rate Link (FRL) training ++ * ++ * Copyright 2026 Michał Kopeć ++ */ ++ ++#ifndef __LINK_HDMI_FRL_TRAINING_H__ ++#define __LINK_HDMI_FRL_TRAINING_H__ ++ ++#include "link_service.h" ++ ++struct dc_link; ++struct link_resource; ++ ++/* ++ * Perform HDMI 2.1 FRL link training. ++ * ++ * @link: ++ * DC link representing the HDMI connection. ++ * ++ * @link_res: ++ * Link resources containing the HPO HDMI FRL link encoder. ++ * ++ * @frl_rate: ++ * FRL rate index as defined by HDMI 2.1 (1–6). ++ * ++ * @lane_count: ++ * Number of FRL lanes (3 or 4). ++ * ++ * Returns: ++ * true - training completed successfully, link is active ++ * false - training failed, link is disabled ++ */ ++bool dc_link_perform_frl_training(struct dc_link *link, ++ const struct link_resource *link_res); ++ ++/* ++ * Disable FRL mode in the sink. Allows fallback to TMDS. ++ */ ++void dc_link_disable_frl(struct dc_link *link); ++ ++/* ++ * Perform HDMI DFM calculation to determine the optimal link settings. ++ * ++ * Returns: ++ * true - Link verification succeeded, link can be configured ++ * false - Link verification failed, link cannot be configured ++ */ ++bool hdmi_decide_link_settings( ++ struct dc_stream_state *stream, ++ struct pipe_ctx *pipe_ctx); ++ ++#endif /* __LINK_HDMI_FRL_TRAINING_H__ */ +diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c +index 29f3a03687b2..953a8b6171ad 100644 +--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c ++++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c +@@ -80,6 +80,7 @@ bool program_hpd_filter(const struct dc_link *link) + case SIGNAL_TYPE_DVI_SINGLE_LINK: + case SIGNAL_TYPE_DVI_DUAL_LINK: + case SIGNAL_TYPE_HDMI_TYPE_A: ++ case SIGNAL_TYPE_HDMI_FRL: + /* Program hpd filter */ + delay_on_connect_in_ms = 500; + delay_on_disconnect_in_ms = 100; +diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +index e853ea110310..b59be1ddd3c8 100644 +--- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +@@ -56,6 +56,8 @@ + #include "dcn30/dcn30_dio_stream_encoder.h" + #include "dcn31/dcn31_hpo_dp_stream_encoder.h" + #include "dcn31/dcn31_hpo_dp_link_encoder.h" ++#include "dcn30/dcn30_hpo_hdmi_stream_encoder.h" ++#include "dcn30/dcn30_hpo_hdmi_link_encoder.h" + #include "dcn31/dcn31_apg.h" + #include "dcn31/dcn31_dio_link_encoder.h" + #include "dcn31/dcn31_vpg.h" +@@ -450,6 +452,18 @@ static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { + DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) + }; + ++static struct dcn30_hpo_hdmi_stream_encoder_registers hpo_hdmi_stream_enc_regs = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_REG_LIST() ++}; ++ ++static const struct dcn30_hpo_hdmi_stream_encoder_shift hpo_hdmi_se_shift = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dcn30_hpo_hdmi_stream_encoder_mask hpo_hdmi_se_mask = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_MASK_SH_LIST(_MASK) ++}; ++ + #define hpo_dp_link_encoder_reg_list(id)\ + [id] = {\ + DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ +@@ -473,6 +487,18 @@ static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { + DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) + }; + ++static struct dcn30_hpo_hdmi_link_encoder_registers hpo_hdmi_link_enc_regs = { ++ DCN3_0_HPO_HDMI_LINK_ENC_REG_LIST() ++}; ++ ++static const struct dcn30_hpo_hdmi_link_encoder_shift hpo_hdmi_le_shift = { ++ DCN3_0_HPO_HDMI_LINK_ENC_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dcn30_hpo_hdmi_link_encoder_mask hpo_hdmi_le_mask = { ++ DCN3_0_HPO_HDMI_LINK_ENC_MASK_SH_LIST(_MASK) ++}; ++ + #define dpp_regs(id)\ + [id] = {\ + DPP_REG_LIST_DCN30(id),\ +@@ -819,6 +845,8 @@ static const struct resource_caps res_cap_dcn31 = { + .num_dig_link_enc = 5, + .num_hpo_dp_stream_encoder = 4, + .num_hpo_dp_link_encoder = 2, ++ .num_hpo_hdmi_stream_encoder = 1, ++ .num_hpo_hdmi_link_encoder = 1, + .num_pll = 5, + .num_dwb = 1, + .num_ddc = 5, +@@ -1304,6 +1332,44 @@ static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( + return &hpo_dp_enc31->base; + } + ++static struct hpo_hdmi_stream_encoder *dcn31_hpo_hdmi_stream_encoder_create( ++ enum engine_id eng_id, ++ struct dc_context *ctx) ++{ ++ struct dcn30_hpo_hdmi_stream_encoder *hpo_hdmi_enc30; ++ struct vpg *vpg; ++ struct afmt *afmt; ++ uint32_t hpo_hdmi_inst; ++ uint32_t vpg_inst; ++ uint32_t afmt_inst; ++ ++ hpo_hdmi_inst = eng_id - ENGINE_ID_HPO_0; ++ ++ /* Mapping of VPG register blocks to HPO HDMI block instance (guessed): ++ * VPG[5] -> HPO_HDMI[0] ++ * AFMT[5] -> HPO_HDMI[0] ++ */ ++ vpg_inst = hpo_hdmi_inst + 5; ++ afmt_inst = hpo_hdmi_inst + 5; ++ ++ /* allocate HPO stream encoder and create VPG sub-block */ ++ hpo_hdmi_enc30 = kzalloc(sizeof(struct dcn30_hpo_hdmi_stream_encoder), GFP_KERNEL); ++ vpg = dcn31_vpg_create(ctx, vpg_inst); ++ afmt = dcn31_afmt_create(ctx, afmt_inst); ++ ++ if (!hpo_hdmi_enc30 || !vpg || !afmt) { ++ kfree(hpo_hdmi_enc30); ++ kfree(vpg); ++ return NULL; ++ } ++ ++ dcn30_hpo_hdmi_stream_encoder_construct(hpo_hdmi_enc30, ctx, hpo_hdmi_inst, ++ vpg, afmt, &hpo_hdmi_stream_enc_regs, ++ &hpo_hdmi_se_shift, &hpo_hdmi_se_mask); ++ ++ return &hpo_hdmi_enc30->base; ++} ++ + static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( + uint8_t inst, + struct dc_context *ctx) +@@ -1322,6 +1388,24 @@ static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( + return &hpo_dp_enc31->base; + } + ++static struct hpo_hdmi_link_encoder *dcn31_hpo_hdmi_link_encoder_create( ++ uint8_t inst, ++ struct dc_context *ctx) ++{ ++ struct dcn30_hpo_hdmi_link_encoder *hpo_hdmi_enc30; ++ ++ /* allocate HPO link encoder */ ++ hpo_hdmi_enc30 = kzalloc(sizeof(struct dcn30_hpo_hdmi_link_encoder), GFP_KERNEL); ++ if (!hpo_hdmi_enc30) ++ return NULL; /* out of memory */ ++ ++ hpo_hdmi_link_encoder31_construct(hpo_hdmi_enc30, ctx, inst, ++ &hpo_hdmi_link_enc_regs, ++ &hpo_hdmi_le_shift, &hpo_hdmi_le_mask); ++ ++ return &hpo_hdmi_enc30->base; ++} ++ + static struct dce_hwseq *dcn31_hwseq_create( + struct dc_context *ctx) + { +@@ -1341,6 +1425,8 @@ static const struct resource_create_funcs res_create_funcs = { + .create_stream_encoder = dcn31_stream_encoder_create, + .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, + .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, ++ .create_hpo_hdmi_stream_encoder = dcn31_hpo_hdmi_stream_encoder_create, ++ .create_hpo_hdmi_link_encoder = dcn31_hpo_hdmi_link_encoder_create, + .create_hwseq = dcn31_hwseq_create, + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c +index 3ccde75a4ecb..3076b1d17098 100644 +--- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c +@@ -59,6 +59,8 @@ + #include "dcn314/dcn314_dio_stream_encoder.h" + #include "dcn31/dcn31_hpo_dp_stream_encoder.h" + #include "dcn31/dcn31_hpo_dp_link_encoder.h" ++#include "dcn30/dcn30_hpo_hdmi_stream_encoder.h" ++#include "dcn30/dcn30_hpo_hdmi_link_encoder.h" + #include "dcn31/dcn31_apg.h" + #include "dcn31/dcn31_vpg.h" + #include "dcn31/dcn31_afmt.h" +@@ -457,6 +459,17 @@ static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { + DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) + }; + ++static struct dcn30_hpo_hdmi_stream_encoder_registers hpo_hdmi_stream_enc_regs = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_REG_LIST() ++}; ++ ++static const struct dcn30_hpo_hdmi_stream_encoder_shift hpo_hdmi_se_shift = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dcn30_hpo_hdmi_stream_encoder_mask hpo_hdmi_se_mask = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_MASK_SH_LIST(_MASK) ++}; + + #define hpo_dp_link_encoder_reg_list(id)\ + [id] = {\ +@@ -479,6 +492,18 @@ static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { + DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) + }; + ++static struct dcn30_hpo_hdmi_link_encoder_registers hpo_hdmi_link_enc_regs = { ++ DCN3_0_HPO_HDMI_LINK_ENC_REG_LIST() ++}; ++ ++static const struct dcn30_hpo_hdmi_link_encoder_shift hpo_hdmi_le_shift = { ++ DCN3_0_HPO_HDMI_LINK_ENC_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dcn30_hpo_hdmi_link_encoder_mask hpo_hdmi_le_mask = { ++ DCN3_0_HPO_HDMI_LINK_ENC_MASK_SH_LIST(_MASK) ++}; ++ + #define dpp_regs(id)\ + [id] = {\ + DPP_REG_LIST_DCN30(id),\ +@@ -831,6 +856,8 @@ static const struct resource_caps res_cap_dcn314 = { + .num_dig_link_enc = 5, + .num_hpo_dp_stream_encoder = 4, + .num_hpo_dp_link_encoder = 2, ++ .num_hpo_hdmi_stream_encoder = 1, ++ .num_hpo_hdmi_link_encoder = 1, + .num_pll = 5, + .num_dwb = 1, + .num_ddc = 5, +@@ -1363,6 +1390,44 @@ static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( + return &hpo_dp_enc31->base; + } + ++static struct hpo_hdmi_stream_encoder *dcn314_hpo_hdmi_stream_encoder_create( ++ enum engine_id eng_id, ++ struct dc_context *ctx) ++{ ++ struct dcn30_hpo_hdmi_stream_encoder *hpo_hdmi_enc30; ++ struct vpg *vpg; ++ struct afmt *afmt; ++ uint32_t hpo_hdmi_inst; ++ uint32_t vpg_inst; ++ uint32_t afmt_inst; ++ ++ hpo_hdmi_inst = eng_id - ENGINE_ID_HPO_0; ++ ++ /* Mapping of VPG register blocks to HPO HDMI block instance (guessed): ++ * VPG[9] -> HPO_HDMI[0] ++ * AFMT[5] -> HPO_HDMI[0] ++ */ ++ vpg_inst = hpo_hdmi_inst + 9; ++ afmt_inst = hpo_hdmi_inst + 5; ++ ++ /* allocate HPO stream encoder and create VPG sub-block */ ++ hpo_hdmi_enc30 = kzalloc(sizeof(struct dcn30_hpo_hdmi_stream_encoder), GFP_KERNEL); ++ vpg = dcn31_vpg_create(ctx, vpg_inst); ++ afmt = dcn31_afmt_create(ctx, afmt_inst); ++ ++ if (!hpo_hdmi_enc30 || !vpg || !afmt) { ++ kfree(hpo_hdmi_enc30); ++ kfree(vpg); ++ return NULL; ++ } ++ ++ dcn30_hpo_hdmi_stream_encoder_construct(hpo_hdmi_enc30, ctx, hpo_hdmi_inst, ++ vpg, afmt, &hpo_hdmi_stream_enc_regs, ++ &hpo_hdmi_se_shift, &hpo_hdmi_se_mask); ++ ++ return &hpo_hdmi_enc30->base; ++} ++ + static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( + uint8_t inst, + struct dc_context *ctx) +@@ -1381,6 +1446,24 @@ static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( + return &hpo_dp_enc31->base; + } + ++static struct hpo_hdmi_link_encoder *dcn314_hpo_hdmi_link_encoder_create( ++ uint8_t inst, ++ struct dc_context *ctx) ++{ ++ struct dcn30_hpo_hdmi_link_encoder *hpo_hdmi_enc30; ++ ++ /* allocate HPO link encoder */ ++ hpo_hdmi_enc30 = kzalloc(sizeof(struct dcn30_hpo_hdmi_link_encoder), GFP_KERNEL); ++ if (!hpo_hdmi_enc30) ++ return NULL; /* out of memory */ ++ ++ hpo_hdmi_link_encoder31_construct(hpo_hdmi_enc30, ctx, inst, ++ &hpo_hdmi_link_enc_regs, ++ &hpo_hdmi_le_shift, &hpo_hdmi_le_mask); ++ ++ return &hpo_hdmi_enc30->base; ++} ++ + static struct dce_hwseq *dcn314_hwseq_create( + struct dc_context *ctx) + { +@@ -1400,6 +1483,8 @@ static const struct resource_create_funcs res_create_funcs = { + .create_stream_encoder = dcn314_stream_encoder_create, + .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, + .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, ++ .create_hpo_hdmi_stream_encoder = dcn314_hpo_hdmi_stream_encoder_create, ++ .create_hpo_hdmi_link_encoder = dcn314_hpo_hdmi_link_encoder_create, + .create_hwseq = dcn314_hwseq_create, + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +index 4e962f522f1b..0f0e34189ccf 100644 +--- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +@@ -55,6 +55,8 @@ + #include "dcn30/dcn30_dio_stream_encoder.h" + #include "dcn31/dcn31_hpo_dp_stream_encoder.h" + #include "dcn31/dcn31_hpo_dp_link_encoder.h" ++#include "dcn30/dcn30_hpo_hdmi_stream_encoder.h" ++#include "dcn30/dcn30_hpo_hdmi_link_encoder.h" + #include "dcn31/dcn31_apg.h" + #include "dcn31/dcn31_dio_link_encoder.h" + #include "dcn31/dcn31_vpg.h" +@@ -452,6 +454,17 @@ static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { + DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) + }; + ++static struct dcn30_hpo_hdmi_stream_encoder_registers hpo_hdmi_stream_enc_regs = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_REG_LIST() ++}; ++ ++static const struct dcn30_hpo_hdmi_stream_encoder_shift hpo_hdmi_se_shift = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dcn30_hpo_hdmi_stream_encoder_mask hpo_hdmi_se_mask = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_MASK_SH_LIST(_MASK) ++}; + + #define hpo_dp_link_encoder_reg_list(id)\ + [id] = {\ +@@ -476,6 +489,18 @@ static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { + DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) + }; + ++static struct dcn30_hpo_hdmi_link_encoder_registers hpo_hdmi_link_enc_regs = { ++ DCN3_0_HPO_HDMI_LINK_ENC_REG_LIST() ++}; ++ ++static const struct dcn30_hpo_hdmi_link_encoder_shift hpo_hdmi_le_shift = { ++ DCN3_0_HPO_HDMI_LINK_ENC_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dcn30_hpo_hdmi_link_encoder_mask hpo_hdmi_le_mask = { ++ DCN3_0_HPO_HDMI_LINK_ENC_MASK_SH_LIST(_MASK) ++}; ++ + #define dpp_regs(id)\ + [id] = {\ + DPP_REG_LIST_DCN30(id),\ +@@ -818,6 +843,8 @@ static const struct resource_caps res_cap_dcn31 = { + .num_dig_link_enc = 5, + .num_hpo_dp_stream_encoder = 4, + .num_hpo_dp_link_encoder = 2, ++ .num_hpo_hdmi_stream_encoder = 1, ++ .num_hpo_hdmi_link_encoder = 1, + .num_pll = 5, + .num_dwb = 1, + .num_ddc = 5, +@@ -1305,6 +1332,44 @@ static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( + return &hpo_dp_enc31->base; + } + ++static struct hpo_hdmi_stream_encoder *dcn315_hpo_hdmi_stream_encoder_create( ++ enum engine_id eng_id, ++ struct dc_context *ctx) ++{ ++ struct dcn30_hpo_hdmi_stream_encoder *hpo_hdmi_enc30; ++ struct vpg *vpg; ++ struct afmt *afmt; ++ uint32_t hpo_hdmi_inst; ++ uint32_t vpg_inst; ++ uint32_t afmt_inst; ++ ++ hpo_hdmi_inst = eng_id - ENGINE_ID_HPO_0; ++ ++ /* Mapping of VPG register blocks to HPO HDMI block instance (guessed): ++ * VPG[5] -> HPO_HDMI[0] ++ * AFMT[5] -> HPO_HDMI[0] ++ */ ++ vpg_inst = hpo_hdmi_inst + 5; ++ afmt_inst = hpo_hdmi_inst + 5; ++ ++ /* allocate HPO stream encoder and create VPG sub-block */ ++ hpo_hdmi_enc30 = kzalloc(sizeof(struct dcn30_hpo_hdmi_stream_encoder), GFP_KERNEL); ++ vpg = dcn31_vpg_create(ctx, vpg_inst); ++ afmt = dcn31_afmt_create(ctx, afmt_inst); ++ ++ if (!hpo_hdmi_enc30 || !vpg || !afmt) { ++ kfree(hpo_hdmi_enc30); ++ kfree(vpg); ++ return NULL; ++ } ++ ++ dcn30_hpo_hdmi_stream_encoder_construct(hpo_hdmi_enc30, ctx, hpo_hdmi_inst, ++ vpg, afmt, &hpo_hdmi_stream_enc_regs, ++ &hpo_hdmi_se_shift, &hpo_hdmi_se_mask); ++ ++ return &hpo_hdmi_enc30->base; ++} ++ + static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( + uint8_t inst, + struct dc_context *ctx) +@@ -1323,6 +1388,24 @@ static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( + return &hpo_dp_enc31->base; + } + ++static struct hpo_hdmi_link_encoder *dcn315_hpo_hdmi_link_encoder_create( ++ uint8_t inst, ++ struct dc_context *ctx) ++{ ++ struct dcn30_hpo_hdmi_link_encoder *hpo_hdmi_enc30; ++ ++ /* allocate HPO link encoder */ ++ hpo_hdmi_enc30 = kzalloc(sizeof(struct dcn30_hpo_hdmi_link_encoder), GFP_KERNEL); ++ if (!hpo_hdmi_enc30) ++ return NULL; /* out of memory */ ++ ++ hpo_hdmi_link_encoder31_construct(hpo_hdmi_enc30, ctx, inst, ++ &hpo_hdmi_link_enc_regs, ++ &hpo_hdmi_le_shift, &hpo_hdmi_le_mask); ++ ++ return &hpo_hdmi_enc30->base; ++} ++ + static struct dce_hwseq *dcn31_hwseq_create( + struct dc_context *ctx) + { +@@ -1342,6 +1425,8 @@ static const struct resource_create_funcs res_create_funcs = { + .create_stream_encoder = dcn315_stream_encoder_create, + .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, + .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, ++ .create_hpo_hdmi_stream_encoder = dcn315_hpo_hdmi_stream_encoder_create, ++ .create_hpo_hdmi_link_encoder = dcn315_hpo_hdmi_link_encoder_create, + .create_hwseq = dcn31_hwseq_create, + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c +index 5a95dd54cb42..7a035748814b 100644 +--- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c +@@ -55,6 +55,8 @@ + #include "dcn30/dcn30_dio_stream_encoder.h" + #include "dcn31/dcn31_hpo_dp_stream_encoder.h" + #include "dcn31/dcn31_hpo_dp_link_encoder.h" ++#include "dcn30/dcn30_hpo_hdmi_stream_encoder.h" ++#include "dcn30/dcn30_hpo_hdmi_link_encoder.h" + #include "dcn31/dcn31_apg.h" + #include "dcn31/dcn31_dio_link_encoder.h" + #include "dcn31/dcn31_vpg.h" +@@ -442,6 +444,17 @@ static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { + DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) + }; + ++static struct dcn30_hpo_hdmi_stream_encoder_registers hpo_hdmi_stream_enc_regs = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_REG_LIST() ++}; ++ ++static const struct dcn30_hpo_hdmi_stream_encoder_shift hpo_hdmi_se_shift = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dcn30_hpo_hdmi_stream_encoder_mask hpo_hdmi_se_mask = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_MASK_SH_LIST(_MASK) ++}; + + #define hpo_dp_link_encoder_reg_list(id)\ + [id] = {\ +@@ -466,6 +479,17 @@ static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { + DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) + }; + ++static struct dcn30_hpo_hdmi_link_encoder_registers hpo_hdmi_link_enc_regs = { ++ DCN3_0_HPO_HDMI_LINK_ENC_REG_LIST() ++}; ++ ++static const struct dcn30_hpo_hdmi_link_encoder_shift hpo_hdmi_le_shift = { ++ DCN3_0_HPO_HDMI_LINK_ENC_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dcn30_hpo_hdmi_link_encoder_mask hpo_hdmi_le_mask = { ++ DCN3_0_HPO_HDMI_LINK_ENC_MASK_SH_LIST(_MASK) ++}; + + #define dpp_regs(id)\ + [id] = {\ +@@ -813,6 +837,8 @@ static const struct resource_caps res_cap_dcn31 = { + .num_dig_link_enc = 5, + .num_hpo_dp_stream_encoder = 4, + .num_hpo_dp_link_encoder = 2, ++ .num_hpo_hdmi_stream_encoder = 1, ++ .num_hpo_hdmi_link_encoder = 1, + .num_pll = 5, + .num_dwb = 1, + .num_ddc = 5, +@@ -1299,6 +1325,44 @@ static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( + return &hpo_dp_enc31->base; + } + ++static struct hpo_hdmi_stream_encoder *dcn316_hpo_hdmi_stream_encoder_create( ++ enum engine_id eng_id, ++ struct dc_context *ctx) ++{ ++ struct dcn30_hpo_hdmi_stream_encoder *hpo_hdmi_enc30; ++ struct vpg *vpg; ++ struct afmt *afmt; ++ uint32_t hpo_hdmi_inst; ++ uint32_t vpg_inst; ++ uint32_t afmt_inst; ++ ++ hpo_hdmi_inst = eng_id - ENGINE_ID_HPO_0; ++ ++ /* Mapping of VPG register blocks to HPO HDMI block instance (guessed): ++ * VPG[5] -> HPO_HDMI[0] ++ * AFMT[5] -> HPO_HDMI[0] ++ */ ++ vpg_inst = hpo_hdmi_inst + 5; ++ afmt_inst = hpo_hdmi_inst + 5; ++ ++ /* allocate HPO stream encoder and create VPG sub-block */ ++ hpo_hdmi_enc30 = kzalloc(sizeof(struct dcn30_hpo_hdmi_stream_encoder), GFP_KERNEL); ++ vpg = dcn31_vpg_create(ctx, vpg_inst); ++ afmt = dcn31_afmt_create(ctx, afmt_inst); ++ ++ if (!hpo_hdmi_enc30 || !vpg || !afmt) { ++ kfree(hpo_hdmi_enc30); ++ kfree(vpg); ++ return NULL; ++ } ++ ++ dcn30_hpo_hdmi_stream_encoder_construct(hpo_hdmi_enc30, ctx, hpo_hdmi_inst, ++ vpg, afmt, &hpo_hdmi_stream_enc_regs, ++ &hpo_hdmi_se_shift, &hpo_hdmi_se_mask); ++ ++ return &hpo_hdmi_enc30->base; ++} ++ + static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( + uint8_t inst, + struct dc_context *ctx) +@@ -1317,6 +1381,23 @@ static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( + return &hpo_dp_enc31->base; + } + ++static struct hpo_hdmi_link_encoder *dcn316_hpo_hdmi_link_encoder_create( ++ uint8_t inst, ++ struct dc_context *ctx) ++{ ++ struct dcn30_hpo_hdmi_link_encoder *hpo_hdmi_enc30; ++ ++ /* allocate HPO link encoder */ ++ hpo_hdmi_enc30 = kzalloc(sizeof(struct dcn30_hpo_hdmi_link_encoder), GFP_KERNEL); ++ if (!hpo_hdmi_enc30) ++ return NULL; /* out of memory */ ++ ++ hpo_hdmi_link_encoder31_construct(hpo_hdmi_enc30, ctx, inst, ++ &hpo_hdmi_link_enc_regs, ++ &hpo_hdmi_le_shift, &hpo_hdmi_le_mask); ++ ++ return &hpo_hdmi_enc30->base; ++} + + static struct dce_hwseq *dcn31_hwseq_create( + struct dc_context *ctx) +@@ -1337,6 +1418,8 @@ static const struct resource_create_funcs res_create_funcs = { + .create_stream_encoder = dcn316_stream_encoder_create, + .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, + .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, ++ .create_hpo_hdmi_stream_encoder = dcn316_hpo_hdmi_stream_encoder_create, ++ .create_hpo_hdmi_link_encoder = dcn316_hpo_hdmi_link_encoder_create, + .create_hwseq = dcn31_hwseq_create, + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +index b276fec3e479..a53570beed60 100644 +--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +@@ -57,6 +57,8 @@ + #include "dcn32/dcn32_dio_stream_encoder.h" + #include "dcn31/dcn31_hpo_dp_stream_encoder.h" + #include "dcn31/dcn31_hpo_dp_link_encoder.h" ++#include "dcn30/dcn30_hpo_hdmi_stream_encoder.h" ++#include "dcn30/dcn30_hpo_hdmi_link_encoder.h" + #include "dcn32/dcn32_hpo_dp_link_encoder.h" + #include "dcn31/dcn31_apg.h" + #include "dcn31/dcn31_dio_link_encoder.h" +@@ -345,6 +347,18 @@ static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { + DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) + }; + ++#define hpo_hdmi_stream_encoder_reg_init()\ ++ DCN3_0_HPO_HDMI_STREAM_ENC_REG_LIST() ++ ++static struct dcn30_hpo_hdmi_stream_encoder_registers hpo_hdmi_stream_enc_regs; ++ ++static const struct dcn30_hpo_hdmi_stream_encoder_shift hpo_hdmi_se_shift = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dcn30_hpo_hdmi_stream_encoder_mask hpo_hdmi_se_mask = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_MASK_SH_LIST(_MASK) ++}; + + #define hpo_dp_link_encoder_reg_init(id)\ + DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) +@@ -363,6 +377,19 @@ static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { + DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) + }; + ++#define hpo_hdmi_link_encoder_reg_init()\ ++ DCN3_0_HPO_HDMI_LINK_ENC_REG_LIST() ++ ++static struct dcn30_hpo_hdmi_link_encoder_registers hpo_hdmi_link_enc_regs; ++ ++static const struct dcn30_hpo_hdmi_link_encoder_shift hpo_hdmi_le_shift = { ++ DCN3_0_HPO_HDMI_LINK_ENC_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dcn30_hpo_hdmi_link_encoder_mask hpo_hdmi_le_mask = { ++ DCN3_0_HPO_HDMI_LINK_ENC_MASK_SH_LIST(_MASK) ++}; ++ + #define dpp_regs_init(id)\ + DPP_REG_LIST_DCN30_COMMON_RI(id) + +@@ -651,6 +678,8 @@ static const struct resource_caps res_cap_dcn32 = { + .num_stream_encoder = 5, + .num_hpo_dp_stream_encoder = 4, + .num_hpo_dp_link_encoder = 2, ++ .num_hpo_hdmi_stream_encoder = 1, ++ .num_hpo_hdmi_link_encoder = 1, + .num_pll = 5, + .num_dwb = 1, + .num_ddc = 5, +@@ -1301,6 +1330,48 @@ static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create( + return &hpo_dp_enc31->base; + } + ++static struct hpo_hdmi_stream_encoder *dcn32_hpo_hdmi_stream_encoder_create( ++ enum engine_id eng_id, ++ struct dc_context *ctx) ++{ ++ struct dcn30_hpo_hdmi_stream_encoder *hpo_hdmi_enc30; ++ struct vpg *vpg; ++ struct afmt *afmt; ++ uint32_t hpo_hdmi_inst; ++ uint32_t vpg_inst; ++ uint32_t afmt_inst; ++ ++ hpo_hdmi_inst = eng_id - ENGINE_ID_HPO_0; ++ ++ /* Mapping of VPG register blocks to HPO HDMI block instance: ++ * VPG[5] -> HPO_HDMI[0] ++ * AFMT[5] -> HPO_HDMI[0] ++ */ ++ vpg_inst = hpo_hdmi_inst + 5; ++ afmt_inst = hpo_hdmi_inst + 5; ++ ++ /* allocate HPO stream encoder and create VPG sub-block */ ++ hpo_hdmi_enc30 = kzalloc(sizeof(struct dcn30_hpo_hdmi_stream_encoder), GFP_KERNEL); ++ vpg = dcn32_vpg_create(ctx, vpg_inst); ++ afmt = dcn32_afmt_create(ctx, afmt_inst); ++ ++ if (!hpo_hdmi_enc30 || !vpg || !afmt) { ++ kfree(hpo_hdmi_enc30); ++ kfree(vpg); ++ return NULL; ++ } ++ ++#undef REG_STRUCT ++#define REG_STRUCT hpo_hdmi_stream_enc_regs ++ hpo_hdmi_stream_encoder_reg_init(), ++ ++ dcn30_hpo_hdmi_stream_encoder_construct(hpo_hdmi_enc30, ctx, hpo_hdmi_inst, ++ vpg, afmt, &hpo_hdmi_stream_enc_regs, ++ &hpo_hdmi_se_shift, &hpo_hdmi_se_mask); ++ ++ return &hpo_hdmi_enc30->base; ++} ++ + static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create( + uint8_t inst, + struct dc_context *ctx) +@@ -1324,6 +1395,28 @@ static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create( + return &hpo_dp_enc31->base; + } + ++static struct hpo_hdmi_link_encoder *dcn32_hpo_hdmi_link_encoder_create( ++ uint8_t inst, ++ struct dc_context *ctx) ++{ ++ struct dcn30_hpo_hdmi_link_encoder *hpo_hdmi_enc30; ++ ++ /* allocate HPO link encoder */ ++ hpo_hdmi_enc30 = kzalloc(sizeof(struct dcn30_hpo_hdmi_link_encoder), GFP_KERNEL); ++ if (!hpo_hdmi_enc30) ++ return NULL; /* out of memory */ ++ ++#undef REG_STRUCT ++#define REG_STRUCT hpo_hdmi_link_enc_regs ++ hpo_hdmi_link_encoder_reg_init(), ++ ++ hpo_hdmi_link_encoder31_construct(hpo_hdmi_enc30, ctx, inst, ++ &hpo_hdmi_link_enc_regs, ++ &hpo_hdmi_le_shift, &hpo_hdmi_le_mask); ++ ++ return &hpo_hdmi_enc30->base; ++} ++ + static struct dce_hwseq *dcn32_hwseq_create( + struct dc_context *ctx) + { +@@ -1347,6 +1440,8 @@ static const struct resource_create_funcs res_create_funcs = { + .create_stream_encoder = dcn32_stream_encoder_create, + .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, + .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, ++ .create_hpo_hdmi_stream_encoder = dcn32_hpo_hdmi_stream_encoder_create, ++ .create_hpo_hdmi_link_encoder = dcn32_hpo_hdmi_link_encoder_create, + .create_hwseq = dcn32_hwseq_create, + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c +index 3466ca34c93f..a5feaf536bc0 100644 +--- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c +@@ -59,6 +59,8 @@ + #include "dcn32/dcn32_dio_stream_encoder.h" + #include "dcn31/dcn31_hpo_dp_stream_encoder.h" + #include "dcn31/dcn31_hpo_dp_link_encoder.h" ++#include "dcn30/dcn30_hpo_hdmi_stream_encoder.h" ++#include "dcn30/dcn30_hpo_hdmi_link_encoder.h" + #include "dcn32/dcn32_hpo_dp_link_encoder.h" + #include "dcn31/dcn31_apg.h" + #include "dcn31/dcn31_dio_link_encoder.h" +@@ -344,6 +346,18 @@ static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { + DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) + }; + ++#define hpo_hdmi_stream_encoder_reg_init()\ ++ DCN3_0_HPO_HDMI_STREAM_ENC_REG_LIST() ++ ++static struct dcn30_hpo_hdmi_stream_encoder_registers hpo_hdmi_stream_enc_regs; ++ ++static const struct dcn30_hpo_hdmi_stream_encoder_shift hpo_hdmi_se_shift = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dcn30_hpo_hdmi_stream_encoder_mask hpo_hdmi_se_mask = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_MASK_SH_LIST(_MASK) ++}; + + #define hpo_dp_link_encoder_reg_init(id)\ + DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) +@@ -362,6 +376,19 @@ static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { + DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) + }; + ++#define hpo_hdmi_link_encoder_reg_init()\ ++ DCN3_0_HPO_HDMI_LINK_ENC_REG_LIST() ++ ++static struct dcn30_hpo_hdmi_link_encoder_registers hpo_hdmi_link_enc_regs; ++ ++static const struct dcn30_hpo_hdmi_link_encoder_shift hpo_hdmi_le_shift = { ++ DCN3_0_HPO_HDMI_LINK_ENC_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dcn30_hpo_hdmi_link_encoder_mask hpo_hdmi_le_mask = { ++ DCN3_0_HPO_HDMI_LINK_ENC_MASK_SH_LIST(_MASK) ++}; ++ + #define dpp_regs_init(id)\ + DPP_REG_LIST_DCN30_COMMON_RI(id) + +@@ -647,6 +674,8 @@ static const struct resource_caps res_cap_dcn321 = { + .num_stream_encoder = 5, + .num_hpo_dp_stream_encoder = 4, + .num_hpo_dp_link_encoder = 2, ++ .num_hpo_hdmi_stream_encoder = 1, ++ .num_hpo_hdmi_link_encoder = 1, + .num_pll = 5, + .num_dwb = 1, + .num_ddc = 5, +@@ -1282,6 +1311,48 @@ static struct hpo_dp_stream_encoder *dcn321_hpo_dp_stream_encoder_create( + return &hpo_dp_enc31->base; + } + ++static struct hpo_hdmi_stream_encoder *dcn321_hpo_hdmi_stream_encoder_create( ++ enum engine_id eng_id, ++ struct dc_context *ctx) ++{ ++ struct dcn30_hpo_hdmi_stream_encoder *hpo_hdmi_enc30; ++ struct vpg *vpg; ++ struct afmt *afmt; ++ uint32_t hpo_hdmi_inst; ++ uint32_t vpg_inst; ++ uint32_t afmt_inst; ++ ++ hpo_hdmi_inst = eng_id - ENGINE_ID_HPO_0; ++ ++ /* Mapping of VPG register blocks to HPO HDMI block instance: ++ * VPG[5] -> HPO_HDMI[0] ++ * AFMT[5] -> HPO_HDMI[0] ++ */ ++ vpg_inst = hpo_hdmi_inst + 5; ++ afmt_inst = hpo_hdmi_inst + 5; ++ ++ /* allocate HPO stream encoder and create VPG sub-block */ ++ hpo_hdmi_enc30 = kzalloc(sizeof(struct dcn30_hpo_hdmi_stream_encoder), GFP_KERNEL); ++ vpg = dcn321_vpg_create(ctx, vpg_inst); ++ afmt = dcn321_afmt_create(ctx, afmt_inst); ++ ++ if (!hpo_hdmi_enc30 || !vpg || !afmt) { ++ kfree(hpo_hdmi_enc30); ++ kfree(vpg); ++ return NULL; ++ } ++ ++#undef REG_STRUCT ++#define REG_STRUCT hpo_hdmi_stream_enc_regs ++ hpo_hdmi_stream_encoder_reg_init(), ++ ++ dcn30_hpo_hdmi_stream_encoder_construct(hpo_hdmi_enc30, ctx, hpo_hdmi_inst, ++ vpg, afmt, &hpo_hdmi_stream_enc_regs, ++ &hpo_hdmi_se_shift, &hpo_hdmi_se_mask); ++ ++ return &hpo_hdmi_enc30->base; ++} ++ + static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create( + uint8_t inst, + struct dc_context *ctx) +@@ -1305,6 +1376,28 @@ static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create( + return &hpo_dp_enc31->base; + } + ++static struct hpo_hdmi_link_encoder *dcn321_hpo_hdmi_link_encoder_create( ++ uint8_t inst, ++ struct dc_context *ctx) ++{ ++ struct dcn30_hpo_hdmi_link_encoder *hpo_hdmi_enc30; ++ ++ /* allocate HPO link encoder */ ++ hpo_hdmi_enc30 = kzalloc(sizeof(struct dcn30_hpo_hdmi_link_encoder), GFP_KERNEL); ++ if (!hpo_hdmi_enc30) ++ return NULL; /* out of memory */ ++ ++#undef REG_STRUCT ++#define REG_STRUCT hpo_hdmi_link_enc_regs ++ hpo_hdmi_link_encoder_reg_init(), ++ ++ hpo_hdmi_link_encoder31_construct(hpo_hdmi_enc30, ctx, inst, ++ &hpo_hdmi_link_enc_regs, ++ &hpo_hdmi_le_shift, &hpo_hdmi_le_mask); ++ ++ return &hpo_hdmi_enc30->base; ++} ++ + static struct dce_hwseq *dcn321_hwseq_create( + struct dc_context *ctx) + { +@@ -1328,6 +1421,8 @@ static const struct resource_create_funcs res_create_funcs = { + .create_stream_encoder = dcn321_stream_encoder_create, + .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create, + .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create, ++ .create_hpo_hdmi_stream_encoder = dcn321_hpo_hdmi_stream_encoder_create, ++ .create_hpo_hdmi_link_encoder = dcn321_hpo_hdmi_link_encoder_create, + .create_hwseq = dcn321_hwseq_create, + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +index 45454a097264..8680acae8f1a 100644 +--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +@@ -60,6 +60,8 @@ + #include "dcn35/dcn35_dio_stream_encoder.h" + #include "dcn31/dcn31_hpo_dp_stream_encoder.h" + #include "dcn31/dcn31_hpo_dp_link_encoder.h" ++#include "dcn30/dcn30_hpo_hdmi_stream_encoder.h" ++#include "dcn30/dcn30_hpo_hdmi_link_encoder.h" + #include "dcn32/dcn32_hpo_dp_link_encoder.h" + #include "link_service.h" + #include "dcn31/dcn31_apg.h" +@@ -365,6 +367,19 @@ static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { + DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) + }; + ++#define hpo_hdmi_stream_encoder_reg_init()\ ++ DCN3_0_HPO_HDMI_STREAM_ENC_REG_LIST() ++ ++static struct dcn30_hpo_hdmi_stream_encoder_registers hpo_hdmi_stream_enc_regs; ++ ++static const struct dcn30_hpo_hdmi_stream_encoder_shift hpo_hdmi_se_shift = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dcn30_hpo_hdmi_stream_encoder_mask hpo_hdmi_se_mask = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_MASK_SH_LIST(_MASK) ++}; ++ + #define hpo_dp_link_encoder_reg_init(id)\ + DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) + /*DCN3_1_RDPCSTX_REG_LIST(0),*/ +@@ -382,6 +397,19 @@ static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { + DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK) + }; + ++#define hpo_hdmi_link_encoder_reg_init()\ ++ DCN3_0_HPO_HDMI_LINK_ENC_REG_LIST() ++ ++static struct dcn30_hpo_hdmi_link_encoder_registers hpo_hdmi_link_enc_regs; ++ ++static const struct dcn30_hpo_hdmi_link_encoder_shift hpo_hdmi_le_shift = { ++ DCN3_0_HPO_HDMI_LINK_ENC_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dcn30_hpo_hdmi_link_encoder_mask hpo_hdmi_le_mask = { ++ DCN3_0_HPO_HDMI_LINK_ENC_MASK_SH_LIST(_MASK) ++}; ++ + #define dpp_regs_init(id)\ + DPP_REG_LIST_DCN35_RI(id) + +@@ -673,6 +701,8 @@ static const struct resource_caps res_cap_dcn35 = { + .num_dig_link_enc = 5, + .num_hpo_dp_stream_encoder = 4, + .num_hpo_dp_link_encoder = 2, ++ .num_hpo_hdmi_stream_encoder = 1, ++ .num_hpo_hdmi_link_encoder = 1, + .num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/ + .num_dwb = 1, + .num_ddc = 5, +@@ -1364,6 +1394,48 @@ static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( + return &hpo_dp_enc31->base; + } + ++static struct hpo_hdmi_stream_encoder *dcn35_hpo_hdmi_stream_encoder_create( ++ enum engine_id eng_id, ++ struct dc_context *ctx) ++{ ++ struct dcn30_hpo_hdmi_stream_encoder *hpo_hdmi_enc30; ++ struct vpg *vpg; ++ struct afmt *afmt; ++ uint32_t hpo_hdmi_inst; ++ uint32_t vpg_inst; ++ uint32_t afmt_inst; ++ ++ hpo_hdmi_inst = eng_id - ENGINE_ID_HPO_0; ++ ++ /* Mapping of VPG register blocks to HPO HDMI block instance: ++ * VPG[5] -> HPO_HDMI[0] ++ * AFMT[5] -> HPO_HDMI[0] ++ */ ++ vpg_inst = hpo_hdmi_inst + 5; ++ afmt_inst = hpo_hdmi_inst + 5; ++ ++ /* allocate HPO stream encoder and create VPG sub-block */ ++ hpo_hdmi_enc30 = kzalloc(sizeof(struct dcn30_hpo_hdmi_stream_encoder), GFP_KERNEL); ++ vpg = dcn31_vpg_create(ctx, vpg_inst); ++ afmt = dcn31_afmt_create(ctx, afmt_inst); ++ ++ if (!hpo_hdmi_enc30 || !vpg || !afmt) { ++ kfree(hpo_hdmi_enc30); ++ kfree(vpg); ++ return NULL; ++ } ++ ++#undef REG_STRUCT ++#define REG_STRUCT hpo_hdmi_stream_enc_regs ++ hpo_hdmi_stream_encoder_reg_init(), ++ ++ dcn30_hpo_hdmi_stream_encoder_construct(hpo_hdmi_enc30, ctx, hpo_hdmi_inst, ++ vpg, afmt, &hpo_hdmi_stream_enc_regs, ++ &hpo_hdmi_se_shift, &hpo_hdmi_se_mask); ++ ++ return &hpo_hdmi_enc30->base; ++} ++ + static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( + uint8_t inst, + struct dc_context *ctx) +@@ -1387,6 +1459,28 @@ static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( + return &hpo_dp_enc31->base; + } + ++static struct hpo_hdmi_link_encoder *dcn35_hpo_hdmi_link_encoder_create( ++ uint8_t inst, ++ struct dc_context *ctx) ++{ ++ struct dcn30_hpo_hdmi_link_encoder *hpo_hdmi_enc30; ++ ++ /* allocate HPO link encoder */ ++ hpo_hdmi_enc30 = kzalloc(sizeof(struct dcn30_hpo_hdmi_link_encoder), GFP_KERNEL); ++ if (!hpo_hdmi_enc30) ++ return NULL; /* out of memory */ ++ ++#undef REG_STRUCT ++#define REG_STRUCT hpo_hdmi_link_enc_regs ++ hpo_hdmi_link_encoder_reg_init(), ++ ++ hpo_hdmi_link_encoder31_construct(hpo_hdmi_enc30, ctx, inst, ++ &hpo_hdmi_link_enc_regs, ++ &hpo_hdmi_le_shift, &hpo_hdmi_le_mask); ++ ++ return &hpo_hdmi_enc30->base; ++} ++ + static struct dce_hwseq *dcn35_hwseq_create( + struct dc_context *ctx) + { +@@ -1410,6 +1504,8 @@ static const struct resource_create_funcs res_create_funcs = { + .create_stream_encoder = dcn35_stream_encoder_create, + .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, + .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, ++ .create_hpo_hdmi_stream_encoder = dcn35_hpo_hdmi_stream_encoder_create, ++ .create_hpo_hdmi_link_encoder = dcn35_hpo_hdmi_link_encoder_create, + .create_hwseq = dcn35_hwseq_create, + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +index e3c587165807..c6d12eb99bc0 100644 +--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +@@ -39,6 +39,8 @@ + #include "dcn35/dcn35_dio_stream_encoder.h" + #include "dcn31/dcn31_hpo_dp_stream_encoder.h" + #include "dcn31/dcn31_hpo_dp_link_encoder.h" ++#include "dcn30/dcn30_hpo_hdmi_stream_encoder.h" ++#include "dcn30/dcn30_hpo_hdmi_link_encoder.h" + #include "dcn32/dcn32_hpo_dp_link_encoder.h" + #include "link_service.h" + #include "dcn31/dcn31_apg.h" +@@ -345,6 +347,19 @@ static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { + DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) + }; + ++#define hpo_hdmi_stream_encoder_reg_init()\ ++ DCN3_0_HPO_HDMI_STREAM_ENC_REG_LIST() ++ ++static struct dcn30_hpo_hdmi_stream_encoder_registers hpo_hdmi_stream_enc_regs; ++ ++static const struct dcn30_hpo_hdmi_stream_encoder_shift hpo_hdmi_se_shift = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dcn30_hpo_hdmi_stream_encoder_mask hpo_hdmi_se_mask = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_MASK_SH_LIST(_MASK) ++}; ++ + #define hpo_dp_link_encoder_reg_init(id)\ + DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) + /*DCN3_1_RDPCSTX_REG_LIST(0),*/ +@@ -362,6 +377,19 @@ static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { + DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK) + }; + ++#define hpo_hdmi_link_encoder_reg_init()\ ++ DCN3_0_HPO_HDMI_LINK_ENC_REG_LIST() ++ ++static struct dcn30_hpo_hdmi_link_encoder_registers hpo_hdmi_link_enc_regs; ++ ++static const struct dcn30_hpo_hdmi_link_encoder_shift hpo_hdmi_le_shift = { ++ DCN3_0_HPO_HDMI_LINK_ENC_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dcn30_hpo_hdmi_link_encoder_mask hpo_hdmi_le_mask = { ++ DCN3_0_HPO_HDMI_LINK_ENC_MASK_SH_LIST(_MASK) ++}; ++ + #define dpp_regs_init(id)\ + DPP_REG_LIST_DCN35_RI(id) + +@@ -653,6 +681,8 @@ static const struct resource_caps res_cap_dcn351 = { + .num_dig_link_enc = 5, + .num_hpo_dp_stream_encoder = 4, + .num_hpo_dp_link_encoder = 2, ++ .num_hpo_hdmi_stream_encoder = 1, ++ .num_hpo_hdmi_link_encoder = 1, + .num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/ + .num_dwb = 1, + .num_ddc = 5, +@@ -1344,6 +1374,48 @@ static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( + return &hpo_dp_enc31->base; + } + ++static struct hpo_hdmi_stream_encoder *dcn35_hpo_hdmi_stream_encoder_create( ++ enum engine_id eng_id, ++ struct dc_context *ctx) ++{ ++ struct dcn30_hpo_hdmi_stream_encoder *hpo_hdmi_enc30; ++ struct vpg *vpg; ++ struct afmt *afmt; ++ uint32_t hpo_hdmi_inst; ++ uint32_t vpg_inst; ++ uint32_t afmt_inst; ++ ++ hpo_hdmi_inst = eng_id - ENGINE_ID_HPO_0; ++ ++ /* Mapping of VPG register blocks to HPO HDMI block instance: ++ * VPG[5] -> HPO_HDMI[0] ++ * AFMT[5] -> HPO_HDMI[0] ++ */ ++ vpg_inst = hpo_hdmi_inst + 5; ++ afmt_inst = hpo_hdmi_inst + 5; ++ ++ /* allocate HPO stream encoder and create VPG sub-block */ ++ hpo_hdmi_enc30 = kzalloc(sizeof(struct dcn30_hpo_hdmi_stream_encoder), GFP_KERNEL); ++ vpg = dcn31_vpg_create(ctx, vpg_inst); ++ afmt = dcn31_afmt_create(ctx, afmt_inst); ++ ++ if (!hpo_hdmi_enc30 || !vpg || !afmt) { ++ kfree(hpo_hdmi_enc30); ++ kfree(vpg); ++ return NULL; ++ } ++ ++#undef REG_STRUCT ++#define REG_STRUCT hpo_hdmi_stream_enc_regs ++ hpo_hdmi_stream_encoder_reg_init(), ++ ++ dcn30_hpo_hdmi_stream_encoder_construct(hpo_hdmi_enc30, ctx, hpo_hdmi_inst, ++ vpg, afmt, &hpo_hdmi_stream_enc_regs, ++ &hpo_hdmi_se_shift, &hpo_hdmi_se_mask); ++ ++ return &hpo_hdmi_enc30->base; ++} ++ + static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( + uint8_t inst, + struct dc_context *ctx) +@@ -1367,6 +1439,28 @@ static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( + return &hpo_dp_enc31->base; + } + ++static struct hpo_hdmi_link_encoder *dcn35_hpo_hdmi_link_encoder_create( ++ uint8_t inst, ++ struct dc_context *ctx) ++{ ++ struct dcn30_hpo_hdmi_link_encoder *hpo_hdmi_enc30; ++ ++ /* allocate HPO link encoder */ ++ hpo_hdmi_enc30 = kzalloc(sizeof(struct dcn30_hpo_hdmi_link_encoder), GFP_KERNEL); ++ if (!hpo_hdmi_enc30) ++ return NULL; /* out of memory */ ++ ++#undef REG_STRUCT ++#define REG_STRUCT hpo_hdmi_link_enc_regs ++ hpo_hdmi_link_encoder_reg_init(), ++ ++ hpo_hdmi_link_encoder31_construct(hpo_hdmi_enc30, ctx, inst, ++ &hpo_hdmi_link_enc_regs, ++ &hpo_hdmi_le_shift, &hpo_hdmi_le_mask); ++ ++ return &hpo_hdmi_enc30->base; ++} ++ + static struct dce_hwseq *dcn351_hwseq_create( + struct dc_context *ctx) + { +@@ -1390,6 +1484,8 @@ static const struct resource_create_funcs res_create_funcs = { + .create_stream_encoder = dcn35_stream_encoder_create, + .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, + .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, ++ .create_hpo_hdmi_stream_encoder = dcn35_hpo_hdmi_stream_encoder_create, ++ .create_hpo_hdmi_link_encoder = dcn35_hpo_hdmi_link_encoder_create, + .create_hwseq = dcn351_hwseq_create, + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c +index 6469d5fe2e6d..74bf9e68830c 100644 +--- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c +@@ -39,6 +39,8 @@ + #include "dcn35/dcn35_dio_stream_encoder.h" + #include "dcn31/dcn31_hpo_dp_stream_encoder.h" + #include "dcn31/dcn31_hpo_dp_link_encoder.h" ++#include "dcn30/dcn30_hpo_hdmi_stream_encoder.h" ++#include "dcn30/dcn30_hpo_hdmi_link_encoder.h" + #include "dcn32/dcn32_hpo_dp_link_encoder.h" + #include "link_service.h" + #include "dcn31/dcn31_apg.h" +@@ -350,6 +352,19 @@ static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { + DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) + }; + ++#define hpo_hdmi_stream_encoder_reg_init()\ ++ DCN3_0_HPO_HDMI_STREAM_ENC_REG_LIST() ++ ++static struct dcn30_hpo_hdmi_stream_encoder_registers hpo_hdmi_stream_enc_regs; ++ ++static const struct dcn30_hpo_hdmi_stream_encoder_shift hpo_hdmi_se_shift = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dcn30_hpo_hdmi_stream_encoder_mask hpo_hdmi_se_mask = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_MASK_SH_LIST(_MASK) ++}; ++ + #define hpo_dp_link_encoder_reg_init(id)\ + DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) + +@@ -363,6 +378,19 @@ static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { + DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK) + }; + ++#define hpo_hdmi_link_encoder_reg_init()\ ++ DCN3_0_HPO_HDMI_LINK_ENC_REG_LIST() ++ ++static struct dcn30_hpo_hdmi_link_encoder_registers hpo_hdmi_link_enc_regs; ++ ++static const struct dcn30_hpo_hdmi_link_encoder_shift hpo_hdmi_le_shift = { ++ DCN3_0_HPO_HDMI_LINK_ENC_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dcn30_hpo_hdmi_link_encoder_mask hpo_hdmi_le_mask = { ++ DCN3_0_HPO_HDMI_LINK_ENC_MASK_SH_LIST(_MASK) ++}; ++ + #define dpp_regs_init(id)\ + DPP_REG_LIST_DCN35_RI(id) + +@@ -654,6 +682,8 @@ static const struct resource_caps res_cap_dcn36 = { + .num_dig_link_enc = 5, + .num_hpo_dp_stream_encoder = 4, + .num_hpo_dp_link_encoder = 2, ++ .num_hpo_hdmi_stream_encoder = 1, ++ .num_hpo_hdmi_link_encoder = 1, + .num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/ + .num_dwb = 1, + .num_ddc = 5, +@@ -1345,6 +1375,48 @@ static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( + return &hpo_dp_enc31->base; + } + ++static struct hpo_hdmi_stream_encoder *dcn36_hpo_hdmi_stream_encoder_create( ++ enum engine_id eng_id, ++ struct dc_context *ctx) ++{ ++ struct dcn30_hpo_hdmi_stream_encoder *hpo_hdmi_enc30; ++ struct vpg *vpg; ++ struct afmt *afmt; ++ uint32_t hpo_hdmi_inst; ++ uint32_t vpg_inst; ++ uint32_t afmt_inst; ++ ++ hpo_hdmi_inst = eng_id - ENGINE_ID_HPO_0; ++ ++ /* Mapping of VPG register blocks to HPO HDMI block instance: ++ * VPG[5] -> HPO_HDMI[0] ++ * AFMT[5] -> HPO_HDMI[0] ++ */ ++ vpg_inst = hpo_hdmi_inst + 5; ++ afmt_inst = hpo_hdmi_inst + 5; ++ ++ /* allocate HPO stream encoder and create VPG sub-block */ ++ hpo_hdmi_enc30 = kzalloc(sizeof(struct dcn30_hpo_hdmi_stream_encoder), GFP_KERNEL); ++ vpg = dcn31_vpg_create(ctx, vpg_inst); ++ afmt = dcn31_afmt_create(ctx, afmt_inst); ++ ++ if (!hpo_hdmi_enc30 || !vpg || !afmt) { ++ kfree(hpo_hdmi_enc30); ++ kfree(vpg); ++ return NULL; ++ } ++ ++#undef REG_STRUCT ++#define REG_STRUCT hpo_hdmi_stream_enc_regs ++ hpo_hdmi_stream_encoder_reg_init(), ++ ++ dcn30_hpo_hdmi_stream_encoder_construct(hpo_hdmi_enc30, ctx, hpo_hdmi_inst, ++ vpg, afmt, &hpo_hdmi_stream_enc_regs, ++ &hpo_hdmi_se_shift, &hpo_hdmi_se_mask); ++ ++ return &hpo_hdmi_enc30->base; ++} ++ + static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( + uint8_t inst, + struct dc_context *ctx) +@@ -1368,6 +1440,28 @@ static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( + return &hpo_dp_enc31->base; + } + ++static struct hpo_hdmi_link_encoder *dcn36_hpo_hdmi_link_encoder_create( ++ uint8_t inst, ++ struct dc_context *ctx) ++{ ++ struct dcn30_hpo_hdmi_link_encoder *hpo_hdmi_enc30; ++ ++ /* allocate HPO link encoder */ ++ hpo_hdmi_enc30 = kzalloc(sizeof(struct dcn30_hpo_hdmi_link_encoder), GFP_KERNEL); ++ if (!hpo_hdmi_enc30) ++ return NULL; /* out of memory */ ++ ++#undef REG_STRUCT ++#define REG_STRUCT hpo_hdmi_link_enc_regs ++ hpo_hdmi_link_encoder_reg_init(), ++ ++ hpo_hdmi_link_encoder31_construct(hpo_hdmi_enc30, ctx, inst, ++ &hpo_hdmi_link_enc_regs, ++ &hpo_hdmi_le_shift, &hpo_hdmi_le_mask); ++ ++ return &hpo_hdmi_enc30->base; ++} ++ + static struct dce_hwseq *dcn36_hwseq_create( + struct dc_context *ctx) + { +@@ -1391,6 +1485,8 @@ static const struct resource_create_funcs res_create_funcs = { + .create_stream_encoder = dcn35_stream_encoder_create, + .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, + .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, ++ .create_hpo_hdmi_stream_encoder = dcn36_hpo_hdmi_stream_encoder_create, ++ .create_hpo_hdmi_link_encoder = dcn36_hpo_hdmi_link_encoder_create, + .create_hwseq = dcn36_hwseq_create, + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +index 1cdbb65da4a3..ef2bd22ffa78 100644 +--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +@@ -36,6 +36,8 @@ + #include "dcn401/dcn401_dio_stream_encoder.h" + #include "dcn31/dcn31_hpo_dp_stream_encoder.h" + #include "dcn31/dcn31_hpo_dp_link_encoder.h" ++#include "dcn30/dcn30_hpo_hdmi_stream_encoder.h" ++#include "dcn30/dcn30_hpo_hdmi_link_encoder.h" + #include "dcn32/dcn32_hpo_dp_link_encoder.h" + #include "dcn31/dcn31_apg.h" + #include "dcn31/dcn31_dio_link_encoder.h" +@@ -325,6 +327,19 @@ static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { + DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) + }; + ++#define hpo_hdmi_stream_encoder_reg_init()\ ++ DCN3_0_HPO_HDMI_STREAM_ENC_REG_LIST() ++ ++static struct dcn30_hpo_hdmi_stream_encoder_registers hpo_hdmi_stream_enc_regs; ++ ++static const struct dcn30_hpo_hdmi_stream_encoder_shift hpo_hdmi_se_shift = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dcn30_hpo_hdmi_stream_encoder_mask hpo_hdmi_se_mask = { ++ DCN3_0_HPO_HDMI_STREAM_ENC_MASK_SH_LIST(_MASK) ++}; ++ + + #define hpo_dp_link_encoder_reg_init(id)\ + DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) +@@ -343,6 +358,19 @@ static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { + DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) + }; + ++#define hpo_hdmi_link_encoder_reg_init()\ ++ DCN3_0_HPO_HDMI_LINK_ENC_REG_LIST() ++ ++static struct dcn30_hpo_hdmi_link_encoder_registers hpo_hdmi_link_enc_regs; ++ ++static const struct dcn30_hpo_hdmi_link_encoder_shift hpo_hdmi_le_shift = { ++ DCN3_0_HPO_HDMI_LINK_ENC_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dcn30_hpo_hdmi_link_encoder_mask hpo_hdmi_le_mask = { ++ DCN3_0_HPO_HDMI_LINK_ENC_MASK_SH_LIST(_MASK) ++}; ++ + #define dpp_regs_init(id)\ + DPP_REG_LIST_DCN401_COMMON_RI(id) + +@@ -642,6 +670,8 @@ static const struct resource_caps res_cap_dcn4_01 = { + .num_stream_encoder = 4, + .num_hpo_dp_stream_encoder = 4, + .num_hpo_dp_link_encoder = 4, ++ .num_hpo_hdmi_stream_encoder = 1, ++ .num_hpo_hdmi_link_encoder = 1, + .num_pll = 4, + .num_dwb = 1, + .num_ddc = 4, +@@ -1230,10 +1260,10 @@ static struct hpo_dp_stream_encoder *dcn401_hpo_dp_stream_encoder_create( + hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; + + /* Mapping of VPG register blocks to HPO DP block instance: +- * VPG[6] -> HPO_DP[0] +- * VPG[7] -> HPO_DP[1] +- * VPG[8] -> HPO_DP[2] +- * VPG[9] -> HPO_DP[3] ++ * VPG[5] -> HPO_DP[0] ++ * VPG[6] -> HPO_DP[1] ++ * VPG[7] -> HPO_DP[2] ++ * VPG[8] -> HPO_DP[3] + */ + vpg_inst = hpo_dp_inst + 5; + +@@ -1272,6 +1302,48 @@ static struct hpo_dp_stream_encoder *dcn401_hpo_dp_stream_encoder_create( + return &hpo_dp_enc31->base; + } + ++static struct hpo_hdmi_stream_encoder *dcn401_hpo_hdmi_stream_encoder_create( ++ enum engine_id eng_id, ++ struct dc_context *ctx) ++{ ++ struct dcn30_hpo_hdmi_stream_encoder *hpo_hdmi_enc30; ++ struct vpg *vpg; ++ struct afmt *afmt; ++ uint32_t hpo_hdmi_inst; ++ uint32_t vpg_inst; ++ uint32_t afmt_inst; ++ ++ hpo_hdmi_inst = eng_id - ENGINE_ID_HPO_0; ++ ++ /* Mapping of VPG register blocks to HPO HDMI block instance (guessed): ++ * VPG[4] -> HPO_HDMI[0] ++ * AFMT[0] -> HPO_HDMI[0] ++ */ ++ vpg_inst = hpo_hdmi_inst + 4; ++ afmt_inst = hpo_hdmi_inst + 4; ++ ++ /* allocate HPO stream encoder and create VPG sub-block */ ++ hpo_hdmi_enc30 = kzalloc(sizeof(struct dcn30_hpo_hdmi_stream_encoder), GFP_KERNEL); ++ vpg = dcn401_vpg_create(ctx, vpg_inst); ++ afmt = dcn401_afmt_create(ctx, afmt_inst); ++ ++ if (!hpo_hdmi_enc30 || !vpg || !afmt) { ++ kfree(hpo_hdmi_enc30); ++ kfree(vpg); ++ return NULL; ++ } ++ ++#undef REG_STRUCT ++#define REG_STRUCT hpo_hdmi_stream_enc_regs ++ hpo_hdmi_stream_encoder_reg_init(), ++ ++ dcn30_hpo_hdmi_stream_encoder_construct(hpo_hdmi_enc30, ctx, hpo_hdmi_inst, ++ vpg, afmt, &hpo_hdmi_stream_enc_regs, ++ &hpo_hdmi_se_shift, &hpo_hdmi_se_mask); ++ ++ return &hpo_hdmi_enc30->base; ++} ++ + static struct hpo_dp_link_encoder *dcn401_hpo_dp_link_encoder_create( + uint8_t inst, + struct dc_context *ctx) +@@ -1297,6 +1369,28 @@ static struct hpo_dp_link_encoder *dcn401_hpo_dp_link_encoder_create( + return &hpo_dp_enc31->base; + } + ++static struct hpo_hdmi_link_encoder *dcn401_hpo_hdmi_link_encoder_create( ++ uint8_t inst, ++ struct dc_context *ctx) ++{ ++ struct dcn30_hpo_hdmi_link_encoder *hpo_hdmi_enc30; ++ ++ /* allocate HPO link encoder */ ++ hpo_hdmi_enc30 = kzalloc(sizeof(struct dcn30_hpo_hdmi_link_encoder), GFP_KERNEL); ++ if (!hpo_hdmi_enc30) ++ return NULL; /* out of memory */ ++ ++#undef REG_STRUCT ++#define REG_STRUCT hpo_hdmi_link_enc_regs ++ hpo_hdmi_link_encoder_reg_init(), ++ ++ hpo_hdmi_link_encoder31_construct(hpo_hdmi_enc30, ctx, inst, ++ &hpo_hdmi_link_enc_regs, ++ &hpo_hdmi_le_shift, &hpo_hdmi_le_mask); ++ ++ return &hpo_hdmi_enc30->base; ++} ++ + static unsigned int dcn401_calc_num_avail_chans_for_mall(struct dc *dc, unsigned int num_chans) + { + unsigned int num_available_chans = 1; +@@ -1344,6 +1438,8 @@ static const struct resource_create_funcs res_create_funcs = { + .create_stream_encoder = dcn401_stream_encoder_create, + .create_hpo_dp_stream_encoder = dcn401_hpo_dp_stream_encoder_create, + .create_hpo_dp_link_encoder = dcn401_hpo_dp_link_encoder_create, ++ .create_hpo_hdmi_stream_encoder = dcn401_hpo_hdmi_stream_encoder_create, ++ .create_hpo_hdmi_link_encoder = dcn401_hpo_hdmi_link_encoder_create, + .create_hwseq = dcn401_hwseq_create, + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h +index 08bec1755617..04860827d762 100644 +--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h ++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h +@@ -627,6 +627,7 @@ unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx); + SR(DPPCLK_DTO_CTRL), DCCG_SRII(DTO_PARAM, DPPCLK, 0), \ + DCCG_SRII(DTO_PARAM, DPPCLK, 1), DCCG_SRII(DTO_PARAM, DPPCLK, 2), \ + DCCG_SRII(DTO_PARAM, DPPCLK, 3), DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0), \ ++ DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0), \ + SR(PHYASYMCLK_CLOCK_CNTL), SR(PHYBSYMCLK_CLOCK_CNTL), \ + SR(PHYCSYMCLK_CLOCK_CNTL), SR(PHYDSYMCLK_CLOCK_CNTL), \ + SR(DPSTREAMCLK_CNTL), SR(HDMISTREAMCLK_CNTL), \ +diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h +index 1c603b12957f..e838f7c1269c 100644 +--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h ++++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h +@@ -36,6 +36,7 @@ + #define DP_BRANCH_DEVICE_ID_006037 0x006037 + #define DP_BRANCH_DEVICE_ID_001CF8 0x001CF8 + #define DP_BRANCH_DEVICE_ID_0060AD 0x0060AD ++#define DP_BRANCH_DEVICE_ID_2B02F0 0x2B02F0 /* Chrontel CH7218 */ + #define DP_BRANCH_HW_REV_10 0x10 + #define DP_BRANCH_HW_REV_20 0x20 + +diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h +index 177acb0574f1..53df1349bea2 100644 +--- a/drivers/gpu/drm/amd/display/include/logger_types.h ++++ b/drivers/gpu/drm/amd/display/include/logger_types.h +@@ -35,7 +35,7 @@ + #define DC_LOG_INFO(...) drm_info((DC_LOGGER)->dev, __VA_ARGS__) + #define DC_LOG_SURFACE(...) pr_debug("[SURFACE]:"__VA_ARGS__) + #define DC_LOG_HW_HOTPLUG(...) drm_dbg((DC_LOGGER)->dev, __VA_ARGS__) +-#define DC_LOG_HW_LINK_TRAINING(...) pr_debug("[HW_LINK_TRAINING]:"__VA_ARGS__) ++#define DC_LOG_HW_LINK_TRAINING(...) pr_info("[HW_LINK_TRAINING]:"__VA_ARGS__) + #define DC_LOG_HW_RESUME_S3(...) drm_dbg((DC_LOGGER)->dev, __VA_ARGS__) + #define DC_LOG_HW_AUDIO(...) pr_debug("[HW_AUDIO]:"__VA_ARGS__) + #define DC_LOG_HW_HPD_IRQ(...) drm_dbg_dp((DC_LOGGER)->dev, __VA_ARGS__) +@@ -46,7 +46,7 @@ + #define DC_LOG_BANDWIDTH_VALIDATION(...) drm_dbg((DC_LOGGER)->dev, __VA_ARGS__) + #define DC_LOG_SYNC(...) drm_dbg((DC_LOGGER)->dev, __VA_ARGS__) + #define DC_LOG_BACKLIGHT(...) drm_dbg_dp((DC_LOGGER)->dev, __VA_ARGS__) +-#define DC_LOG_DETECTION_EDID_PARSER(...) drm_dbg((DC_LOGGER)->dev, __VA_ARGS__) ++#define DC_LOG_DETECTION_EDID_PARSER(...) drm_info((DC_LOGGER)->dev, __VA_ARGS__) + #define DC_LOG_DETECTION_DP_CAPS(...) drm_dbg_dp((DC_LOGGER)->dev, __VA_ARGS__) + #define DC_LOG_DML(...) pr_debug("[DML]:"__VA_ARGS__) + #define DC_LOG_EVENT_MODE_SET(...) drm_dbg_kms((DC_LOGGER)->dev, __VA_ARGS__) +diff --git a/drivers/gpu/drm/amd/display/include/signal_types.h b/drivers/gpu/drm/amd/display/include/signal_types.h +index 3a2c2d2fb629..662e6c963256 100644 +--- a/drivers/gpu/drm/amd/display/include/signal_types.h ++++ b/drivers/gpu/drm/amd/display/include/signal_types.h +@@ -42,6 +42,7 @@ enum signal_type { + SIGNAL_TYPE_DISPLAY_PORT_MST = (1 << 6), + SIGNAL_TYPE_EDP = (1 << 7), + SIGNAL_TYPE_VIRTUAL = (1 << 9), /* Virtual Display */ ++ SIGNAL_TYPE_HDMI_FRL = (1 << 10), + }; + + static inline const char *signal_type_to_string(const int type) +@@ -65,6 +66,8 @@ static inline const char *signal_type_to_string(const int type) + return "Display Port: MST"; + case SIGNAL_TYPE_EDP: + return "Embedded Display Port"; ++ case SIGNAL_TYPE_HDMI_FRL: ++ return "HDMI: FRL"; + case SIGNAL_TYPE_VIRTUAL: + return "Virtual"; + default: +@@ -78,9 +81,15 @@ static inline bool dc_is_hdmi_tmds_signal(enum signal_type signal) + return (signal == SIGNAL_TYPE_HDMI_TYPE_A); + } + ++static inline bool dc_is_hdmi_frl_signal(enum signal_type signal) ++{ ++ return (signal == SIGNAL_TYPE_HDMI_FRL); ++} ++ + static inline bool dc_is_hdmi_signal(enum signal_type signal) + { +- return (signal == SIGNAL_TYPE_HDMI_TYPE_A); ++ return (signal == SIGNAL_TYPE_HDMI_TYPE_A || ++ signal == SIGNAL_TYPE_HDMI_FRL); + } + + static inline bool dc_is_dp_sst_signal(enum signal_type signal) +diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +index 1aae46d703ba..db197cf048e1 100644 +--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c ++++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +@@ -27,6 +27,7 @@ + #include "dc.h" + #include "mod_freesync.h" + #include "core_types.h" ++#include "mod_info_packet.h" + + #define MOD_FREESYNC_MAX_CONCURRENT_STREAMS 32 + +@@ -955,6 +956,9 @@ void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync, + return; + + switch (packet_type) { ++ case PACKET_TYPE_VTEM: ++ mod_build_vtem_infopacket(stream, vrr, infopacket); ++ break; + case PACKET_TYPE_FS_V3: + build_vrr_infopacket_v3(stream->signal, vrr, app_tf, infopacket, stream->freesync_on_desktop); + break; +diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c +index ca402ddcdacc..d6cba97f6375 100644 +--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c ++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c +@@ -584,6 +584,7 @@ enum mod_hdcp_operation_mode mod_hdcp_signal_type_to_operation_mode( + switch (signal) { + case SIGNAL_TYPE_DVI_SINGLE_LINK: + case SIGNAL_TYPE_HDMI_TYPE_A: ++ case SIGNAL_TYPE_HDMI_FRL: + mode = MOD_HDCP_MODE_DEFAULT; + break; + case SIGNAL_TYPE_EDP: +diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h +index ddd64b7e4c04..9d767e6fc977 100644 +--- a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h ++++ b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h +@@ -33,11 +33,13 @@ struct dc_stream_state; + struct dc_info_packet; + struct mod_vrr_params; + ++#define VTEM_BRR_MAX 1023 ++ + void set_vsc_packet_colorimetry_data( + const struct dc_stream_state *stream, + struct dc_info_packet *info_packet, + enum dc_color_space cs, +- enum color_transfer_func tf); ++ enum color_transfer_func tf);\ + + void mod_build_vsc_infopacket(const struct dc_stream_state *stream, + struct dc_info_packet *info_packet, +@@ -47,12 +49,17 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream, + void mod_build_hf_vsif_infopacket(const struct dc_stream_state *stream, + struct dc_info_packet *info_packet); + ++void mod_build_vtem_infopacket(const struct dc_stream_state *stream, ++ const struct mod_vrr_params *vrr, ++ struct dc_info_packet *infopacket); ++ + enum adaptive_sync_type { +- ADAPTIVE_SYNC_TYPE_NONE = 0, +- ADAPTIVE_SYNC_TYPE_DP = 1, +- FREESYNC_TYPE_PCON_IN_WHITELIST = 2, +- FREESYNC_TYPE_PCON_NOT_IN_WHITELIST = 3, +- ADAPTIVE_SYNC_TYPE_EDP = 4, ++ ADAPTIVE_SYNC_TYPE_NONE = 0, ++ ADAPTIVE_SYNC_TYPE_DP = 1, ++ ADAPTIVE_SYNC_TYPE_PCON_ALLOWED = 2, ++ ADAPTIVE_SYNC_TYPE_PCON_NOT_ALLOWED = 3, ++ ADAPTIVE_SYNC_TYPE_EDP = 4, ++ ADAPTIVE_SYNC_TYPE_HDMI = 5, + }; + + enum adaptive_sync_sdp_version { +diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c +index 00473c6284d5..7dcea43ba2c4 100644 +--- a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c ++++ b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c +@@ -48,8 +48,12 @@ enum vsc_packet_revision { + vsc_packet_rev7 = 7, + }; + ++#define HDMI_INFOFRAME_TYPE_EMP 0x7F + #define HDMI_INFOFRAME_TYPE_VENDOR 0x81 +-#define HF_VSIF_VERSION 1 ++#define HDMI_INFOFRAME_LENGTH_MASK 0x1F ++#define HF_VSIF_VERSION 1 ++#define HF_VSIF_3D_BIT 0 ++#define HF_VSIF_ALLM_BIT 1 + + // VTEM Byte Offset + #define VTEM_PB0 0 +@@ -60,64 +64,51 @@ enum vsc_packet_revision { + #define VTEM_PB5 5 + #define VTEM_PB6 6 + +-#define VTEM_MD0 7 +-#define VTEM_MD1 8 +-#define VTEM_MD2 9 +-#define VTEM_MD3 10 +- +- +-// VTEM Byte Masks +-//PB0 +-#define MASK_VTEM_PB0__RESERVED0 0x01 +-#define MASK_VTEM_PB0__SYNC 0x02 +-#define MASK_VTEM_PB0__VFR 0x04 +-#define MASK_VTEM_PB0__AFR 0x08 +-#define MASK_VTEM_PB0__DS_TYPE 0x30 +- //0: Periodic pseudo-static EM Data Set +- //1: Periodic dynamic EM Data Set +- //2: Unique EM Data Set +- //3: Reserved +-#define MASK_VTEM_PB0__END 0x40 +-#define MASK_VTEM_PB0__NEW 0x80 +- +-//PB1 +-#define MASK_VTEM_PB1__RESERVED1 0xFF +- +-//PB2 +-#define MASK_VTEM_PB2__ORGANIZATION_ID 0xFF +- //0: This is a Vendor Specific EM Data Set +- //1: This EM Data Set is defined by This Specification (HDMI 2.1 r102.clean) +- //2: This EM Data Set is defined by CTA-861-G +- //3: This EM Data Set is defined by VESA +-//PB3 +-#define MASK_VTEM_PB3__DATA_SET_TAG_MSB 0xFF +-//PB4 +-#define MASK_VTEM_PB4__DATA_SET_TAG_LSB 0xFF +-//PB5 +-#define MASK_VTEM_PB5__DATA_SET_LENGTH_MSB 0xFF +-//PB6 +-#define MASK_VTEM_PB6__DATA_SET_LENGTH_LSB 0xFF +- +- +- +-//PB7-27 (20 bytes): +-//PB7 = MD0 +-#define MASK_VTEM_MD0__VRR_EN 0x01 +-#define MASK_VTEM_MD0__M_CONST 0x02 +-#define MASK_VTEM_MD0__QMS_EN 0x04 +-#define MASK_VTEM_MD0__RESERVED2 0x08 +-#define MASK_VTEM_MD0__FVA_FACTOR_M1 0xF0 +- +-//MD1 +-#define MASK_VTEM_MD1__BASE_VFRONT 0xFF +- +-//MD2 +-#define MASK_VTEM_MD2__BASE_REFRESH_RATE_98 0x03 +-#define MASK_VTEM_MD2__RB 0x04 +-#define MASK_VTEM_MD2__NEXT_TFR 0xF8 +- +-//MD3 +-#define MASK_VTEM_MD3__BASE_REFRESH_RATE_07 0xFF ++#define VTEM_ORG_ID 1 ++#define VTEM_DATA_SET_TAG 1 ++#define VTEM_DATA_SET_LENGTH 4 ++ ++#define VTEM_M_CONST 0 ++#define VTEM_FVA_FACTOR 0 ++ ++#define VTEM_BRR_MASK_UPPER 0x03 ++#define VTEM_BRR_MASK_LOWER 0xFF ++ ++/* VTEM Byte Offset */ ++#define VTEM_PB0 0 ++#define VTEM_PB1 1 ++#define VTEM_PB2 2 ++#define VTEM_PB3 3 ++#define VTEM_PB4 4 ++#define VTEM_PB5 5 ++#define VTEM_PB6 6 ++ ++#define VTEM_MD0 7 ++#define VTEM_MD1 8 ++#define VTEM_MD2 9 ++#define VTEM_MD3 10 ++ ++/* Extended Metadata Packet */ ++/* Header */ ++#define EMP_LAST_BIT 6 ++#define EMP_FIRST_BIT 7 ++/* PB0 */ ++#define EMP_SNC_BIT 1 ++#define EMP_VFR_BIT 2 ++#define EMP_AFR_BIT 3 ++#define EMP_DST_BIT 4 ++#define EMP_END_BIT 6 ++#define EMP_NEW_BIT 7 ++/* PB7 = MD0 */ ++#define VTEM_VRR_BIT 0 ++#define VTEM_M_CONST_BIT 1 ++#define VTEM_FVA_BIT 4 ++/* MD1 Base_Vfront */ ++/* MD2 */ ++#define VTEM_BRR_UPPER_BIT 0 ++#define VTEM_RB_BIT 2 ++/* MD3 BRR Lower */ ++ + + enum ColorimetryRGBDP { + ColorimetryRGB_DP_sRGB = 0, +@@ -496,9 +487,29 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream, + } + } + ++static bool is_hdmi_vic_mode(const struct dc_stream_state *stream) ++{ ++ if (stream->timing.hdmi_vic == 0) ++ return false; ++ ++ if (stream->timing.h_total < 3840 || ++ stream->timing.v_total < 2160) ++ return false; ++ ++ /* 3D/ALLM forces HDMI VIC -> CTA VIC translation */ ++ if (stream->view_format != VIEW_3D_FORMAT_NONE) ++ return false; ++ ++ if (stream->hdmi_allm_active) ++ return false; ++ ++ return true; ++} ++ + /** + * mod_build_hf_vsif_infopacket - Prepare HDMI Vendor Specific info frame. + * Follows HDMI Spec to build up Vendor Specific info frame ++ * Conforms to h14b-vsif or hf-vsif based on the capabilities + * + * @stream: contains data we may need to construct VSIF (i.e. timing_3d_format, etc.) + * @info_packet: output structure where to store VSIF +@@ -506,63 +517,76 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream, + void mod_build_hf_vsif_infopacket(const struct dc_stream_state *stream, + struct dc_info_packet *info_packet) + { +- unsigned int length = 5; + bool hdmi_vic_mode = false; ++ bool allm = false; ++ bool stereo = false; + uint8_t checksum = 0; +- uint32_t i = 0; ++ uint8_t offset = 0; ++ uint8_t i = 0; ++ uint8_t length = 5; ++ uint32_t oui = HDMI_IEEE_OUI; + enum dc_timing_3d_format format; + + info_packet->valid = false; +- format = stream->timing.timing_3d_format; +- if (stream->view_format == VIEW_3D_FORMAT_NONE) +- format = TIMING_3D_FORMAT_NONE; + +- if (stream->timing.hdmi_vic != 0 +- && stream->timing.h_total >= 3840 +- && stream->timing.v_total >= 2160 +- && format == TIMING_3D_FORMAT_NONE) +- hdmi_vic_mode = true; ++ allm = stream->hdmi_allm_active; ++ format = stream->view_format == VIEW_3D_FORMAT_NONE ? ++ TIMING_3D_FORMAT_NONE : ++ stream->timing.timing_3d_format; ++ stereo = format != TIMING_3D_FORMAT_NONE; ++ hdmi_vic_mode = is_hdmi_vic_mode(stream); + +- if ((format == TIMING_3D_FORMAT_NONE) && !hdmi_vic_mode) ++ if (!stereo && !hdmi_vic_mode && !allm) + return; + +- info_packet->sb[1] = 0x03; +- info_packet->sb[2] = 0x0C; +- info_packet->sb[3] = 0x00; ++ if (allm) ++ oui = HDMI_FORUM_IEEE_OUI; + +- if (format != TIMING_3D_FORMAT_NONE) +- info_packet->sb[4] = (2 << 5); ++ info_packet->sb[1] = oui & 0xFF; ++ info_packet->sb[2] = (oui >> 8) & 0xFF; ++ info_packet->sb[3] = (oui >> 16) & 0xFF; + +- else if (hdmi_vic_mode) +- info_packet->sb[4] = (1 << 5); ++ if (oui == HDMI_FORUM_IEEE_OUI) { ++ offset = 2; ++ length += 2; ++ info_packet->sb[4] = HF_VSIF_VERSION; ++ info_packet->sb[5] = stereo << HF_VSIF_3D_BIT; ++ info_packet->sb[5] |= allm << HF_VSIF_ALLM_BIT; ++ } + +- switch (format) { +- case TIMING_3D_FORMAT_HW_FRAME_PACKING: +- case TIMING_3D_FORMAT_SW_FRAME_PACKING: +- info_packet->sb[5] = (0x0 << 4); +- break; ++ if (stereo) { ++ info_packet->sb[4 + offset] = (2 << 5); + +- case TIMING_3D_FORMAT_SIDE_BY_SIDE: +- case TIMING_3D_FORMAT_SBS_SW_PACKED: +- info_packet->sb[5] = (0x8 << 4); +- length = 6; +- break; ++ switch (format) { ++ case TIMING_3D_FORMAT_HW_FRAME_PACKING: ++ case TIMING_3D_FORMAT_SW_FRAME_PACKING: ++ info_packet->sb[5 + offset] = (0x0 << 4); ++ break; + +- case TIMING_3D_FORMAT_TOP_AND_BOTTOM: +- case TIMING_3D_FORMAT_TB_SW_PACKED: +- info_packet->sb[5] = (0x6 << 4); +- break; ++ case TIMING_3D_FORMAT_SIDE_BY_SIDE: ++ case TIMING_3D_FORMAT_SBS_SW_PACKED: ++ info_packet->sb[5 + offset] = (0x8 << 4); ++ ++length; ++ break; + +- default: +- break; +- } ++ case TIMING_3D_FORMAT_TOP_AND_BOTTOM: ++ case TIMING_3D_FORMAT_TB_SW_PACKED: ++ info_packet->sb[5 + offset] = (0x6 << 4); ++ break; ++ ++ default: ++ break; ++ } + +- if (hdmi_vic_mode) ++ /* Doesn't need the offset as it can't be used with hf-vsif */ ++ } else if (hdmi_vic_mode) { ++ info_packet->sb[4] = (1 << 5); + info_packet->sb[5] = stream->timing.hdmi_vic; ++ } + + info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; + info_packet->hb1 = 0x01; +- info_packet->hb2 = (uint8_t) (length); ++ info_packet->hb2 = length & HDMI_INFOFRAME_LENGTH_MASK; + + checksum += info_packet->hb0; + checksum += info_packet->hb1; +@@ -576,6 +600,92 @@ void mod_build_hf_vsif_infopacket(const struct dc_stream_state *stream, + info_packet->valid = true; + } + ++static void build_vtem_infopacket_header(struct dc_info_packet *infopacket) ++{ ++ uint8_t pb0 = 0; ++ ++ /* might need logic in the future */ ++ pb0 |= 0 << EMP_SNC_BIT; ++ pb0 |= 1 << EMP_VFR_BIT; ++ pb0 |= 0 << EMP_AFR_BIT; ++ pb0 |= 0 << EMP_DST_BIT; ++ pb0 |= 0 << EMP_END_BIT; ++ pb0 |= 1 << EMP_NEW_BIT; ++ ++ infopacket->hb0 = HDMI_INFOFRAME_TYPE_EMP; ++ infopacket->hb1 = (1 << EMP_FIRST_BIT) | (1 << EMP_LAST_BIT); ++ infopacket->hb2 = 0; // sequence ++ ++ infopacket->sb[VTEM_PB0] = pb0; ++ infopacket->sb[VTEM_PB2] = VTEM_ORG_ID; ++ infopacket->sb[VTEM_PB4] = VTEM_DATA_SET_TAG; ++ infopacket->sb[VTEM_PB6] = VTEM_DATA_SET_LENGTH; ++} ++ ++static void build_vtem_infopacket_data(const struct dc_stream_state *stream, ++ const struct mod_vrr_params *vrr, ++ struct dc_info_packet *infopacket) ++{ ++ unsigned int hblank = 0; ++ unsigned int brr = 0; ++ bool vrr_active = false; ++ bool rb = false; ++ ++ /* ++ * Enables FreeSync-like behavior by keeping HDMI VRR signalling active ++ * in fixed refresh rate conditions like normal desktop work/web browsing. ++ * Functinally behaves like non-VRR mode by keeping the actual refresh ++ * rate fixed. ++ */ ++ if (stream->freesync_on_desktop) { ++ vrr_active = vrr->state != VRR_STATE_DISABLED && ++ vrr->state != VRR_STATE_UNSUPPORTED; ++ } else { ++ vrr_active = vrr->state == VRR_STATE_ACTIVE_VARIABLE || ++ vrr->state == VRR_STATE_ACTIVE_FIXED; ++ } ++ ++ infopacket->sb[VTEM_MD0] = VTEM_M_CONST << VTEM_M_CONST_BIT; ++ infopacket->sb[VTEM_MD0] |= VTEM_FVA_FACTOR << VTEM_FVA_BIT; ++ infopacket->sb[VTEM_MD0] |= vrr_active << VTEM_VRR_BIT; ++ ++ infopacket->sb[VTEM_MD1] = 0; ++ infopacket->sb[VTEM_MD2] = 0; ++ infopacket->sb[VTEM_MD3] = 0; ++ ++ if (!vrr_active || is_hdmi_vic_mode(stream)) ++ return; ++ /* ++ * In accordance with CVT 1.2 and CVT 2.1: ++ * Reduced Blanking standard defines a fixed value of ++ * 160 for hblank, further reduced to 80 in RB2. RB3 uses ++ * fixed hblank of 80 pixels + up to 120 additional pixels ++ * in 8-pixel steps. ++ */ ++ hblank = stream->timing.h_total - stream->timing.h_addressable; ++ rb = (hblank >= 80 && hblank <= 200 && hblank % 8 == 0); ++ brr = div_u64(mod_freesync_calc_nominal_field_rate(stream), 1000000); ++ ++ if (brr > VTEM_BRR_MAX) { ++ infopacket->valid = false; ++ return; ++ } ++ ++ infopacket->sb[VTEM_MD1] = (uint8_t) stream->timing.v_front_porch; ++ infopacket->sb[VTEM_MD2] = rb << VTEM_RB_BIT; ++ infopacket->sb[VTEM_MD2] |= (brr >> 8) & VTEM_BRR_MASK_UPPER; ++ infopacket->sb[VTEM_MD3] = brr & VTEM_BRR_MASK_LOWER; ++} ++ ++void mod_build_vtem_infopacket(const struct dc_stream_state *stream, ++ const struct mod_vrr_params *vrr, ++ struct dc_info_packet *infopacket) ++{ ++ infopacket->valid = true; ++ build_vtem_infopacket_header(infopacket); ++ build_vtem_infopacket_data(stream, vrr, infopacket); ++} ++ + void mod_build_adaptive_sync_infopacket(const struct dc_stream_state *stream, + enum adaptive_sync_type asType, + const struct AS_Df_params *param, +@@ -590,7 +700,7 @@ void mod_build_adaptive_sync_infopacket(const struct dc_stream_state *stream, + if (stream != NULL) + mod_build_adaptive_sync_infopacket_v2(stream, param, info_packet); + break; +- case FREESYNC_TYPE_PCON_IN_WHITELIST: ++ case ADAPTIVE_SYNC_TYPE_PCON_ALLOWED: + case ADAPTIVE_SYNC_TYPE_EDP: + if (stream && stream->link->replay_settings.config.replay_supported && + stream->link->replay_settings.config.replay_version == DC_VESA_PANEL_REPLAY) +@@ -599,7 +709,8 @@ void mod_build_adaptive_sync_infopacket(const struct dc_stream_state *stream, + mod_build_adaptive_sync_infopacket_v1(info_packet); + break; + case ADAPTIVE_SYNC_TYPE_NONE: +- case FREESYNC_TYPE_PCON_NOT_IN_WHITELIST: ++ case ADAPTIVE_SYNC_TYPE_PCON_NOT_ALLOWED: ++ case ADAPTIVE_SYNC_TYPE_HDMI: + default: + break; + } +diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h +index ac2d3701e2bd..894e1e738ce0 100644 +--- a/drivers/gpu/drm/amd/include/amd_shared.h ++++ b/drivers/gpu/drm/amd/include/amd_shared.h +@@ -412,6 +412,12 @@ enum DC_DEBUG_MASK { + * @DC_SKIP_DETECTION_LT: (0x200000) If set, skip detection link training + */ + DC_SKIP_DETECTION_LT = 0x200000, ++ ++ /** ++ * @DC_OVERRIDE_PCON_VRR_ID_CHECK: (0x400000) If set, always return true if checking for ++ * PCON VRR compatibility and print it's ID in kernel log. ++ */ ++ DC_OVERRIDE_PCON_VRR_ID_CHECK = 0x400000, + }; + + enum amd_dpm_forced_level; +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h +index 7fd906f10803..7de1451745cd 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h +@@ -12908,6 +12908,120 @@ + #define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 3 + + ++// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec ++// base address: 0x2656c ++#define regHDMI_LINK_ENC_CONTROL 0x095b ++#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 ++#define regHDMI_LINK_ENC_CLK_CTRL 0x095c ++#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 ++ ++ ++// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec ++// base address: 0x26594 ++#define regHDMI_FRL_ENC_CONFIG 0x0965 ++#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 ++#define regHDMI_FRL_ENC_CONFIG2 0x0966 ++#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 ++#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 ++#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 ++#define regHDMI_FRL_ENC_MEM_CTRL 0x0968 ++#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 ++ ++ ++// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec ++// base address: 0x2634c ++#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 ++#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 ++#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 ++ ++ ++// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec ++// base address: 0x2637c ++#define regHDMI_TB_ENC_CONTROL 0x08df ++#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 ++#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 ++#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 ++#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 ++#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 ++#define regHDMI_TB_ENC_GC_CONTROL 0x08e5 ++#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 ++#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea ++#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb ++#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec ++#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed ++#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee ++#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef ++#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 ++#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_DB_CONTROL 0x08f1 ++#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_32_0 0x08f2 ++#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_32_1 0x08f3 ++#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_44_0 0x08f4 ++#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_44_1 0x08f5 ++#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_48_0 0x08f6 ++#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_48_1 0x08f7 ++#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 ++#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 ++#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb ++#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_MEM_CTRL 0x08fe ++#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 ++#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff ++#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 ++#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 ++#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 ++#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 ++#define regHDMI_TB_ENC_CRC_CNTL 0x0903 ++#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 ++#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 ++#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ENCRYPTION_CONTROL 0x0907 ++#define regHDMI_TB_ENC_ENCRYPTION_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_MODE 0x0908 ++#define regHDMI_TB_ENC_MODE_BASE_IDX 3 ++#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 ++#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 ++#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a ++#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 ++ ++ + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec + // base address: 0x2646c + #define regAFMT5_AFMT_VBI_PACKET_CONTROL 0x091c +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h +index 07fbfafe6056..21ae70bf0eee 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h +@@ -48392,6 +48392,507 @@ + #define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L ++ ++ ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 ++#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L ++ ++ ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L ++#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 ++#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE__SHIFT 0x8 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE_MASK 0x00000300L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L ++ ++ ++#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 ++#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc ++#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L ++#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L ++#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L ++#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL ++#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L ++#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL ++#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L ++#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL ++#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L ++#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L ++#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_ENABLE__SHIFT 0x0 ++#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_WHEN_AVMUTE__SHIFT 0x4 ++#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_ENABLE_MASK 0x00000001L ++#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_WHEN_AVMUTE_MASK 0x00000010L ++#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 ++#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 ++#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L ++#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L ++#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 ++#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L ++#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 ++#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL ++ ++ ++ + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec + //AFMT5_AFMT_VBI_PACKET_CONTROL + #define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_offset.h +index 20a6ee7adeef..3c601d1cd894 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_offset.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_offset.h +@@ -14561,6 +14561,40 @@ + #define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 3 + + ++// addressBlock: dcn_dcec_hpo_hdmi_link_enc0_dispdec ++// base address: 0x2656c ++#define regHDMI_LINK_ENC_CONTROL 0x095b ++#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 ++#define regHDMI_LINK_ENC_CLK_CTRL 0x095c ++#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 ++ ++ ++// addressBlock: dcn_dcec_hpo_hdmi_frl_enc0_dispdec ++// base address: 0x26594 ++#define regHDMI_FRL_ENC_CONFIG 0x0965 ++#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 ++#define regHDMI_FRL_ENC_CONFIG2 0x0966 ++#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 ++#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 ++#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 ++#define regHDMI_FRL_ENC_MEM_CTRL 0x0968 ++#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 ++ ++ ++// addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_dispdec ++// base address: 0x2634c ++#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 ++#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 ++#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 ++ ++ + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec + // base address: 0x2646c + #define regAFMT5_AFMT_VBI_PACKET_CONTROL 0x091c +@@ -14634,6 +14668,85 @@ + #define regDME9_DME_MEMORY_CONTROL 0x093d + #define regDME9_DME_MEMORY_CONTROL_BASE_IDX 3 + ++// addressBlock: dcn_dcec_hpo_hdmi_tb_enc0_dispdec ++// base address: 0x2637c ++#define regHDMI_TB_ENC_CONTROL 0x08df ++#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 ++#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 ++#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 ++#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 ++#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 ++#define regHDMI_TB_ENC_GC_CONTROL 0x08e5 ++#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 ++#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea ++#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb ++#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec ++#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed ++#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee ++#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef ++#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 ++#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_DB_CONTROL 0x08f1 ++#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_32_0 0x08f2 ++#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_32_1 0x08f3 ++#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_44_0 0x08f4 ++#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_44_1 0x08f5 ++#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_48_0 0x08f6 ++#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_48_1 0x08f7 ++#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 ++#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 ++#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb ++#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_MEM_CTRL 0x08fe ++#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 ++#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff ++#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 ++#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 ++#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 ++#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 ++#define regHDMI_TB_ENC_CRC_CNTL 0x0903 ++#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 ++#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 ++#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ENCRYPTION_CONTROL 0x0907 ++#define regHDMI_TB_ENC_ENCRYPTION_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_MODE 0x0908 ++#define regHDMI_TB_ENC_MODE_BASE_IDX 3 ++#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 ++#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 ++#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a ++#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 ++ + + // addressBlock: dce_dc_hpo_hpo_top_dispdec + // base address: 0x2790c +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_sh_mask.h +index d3d98d43287c..714d26c64427 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_sh_mask.h +@@ -59877,6 +59877,122 @@ + #define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + ++// addressBlock: dcn_dcec_hpo_hdmi_link_enc0_dispdec ++//HDMI_LINK_ENC_CONTROL ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L ++//HDMI_LINK_ENC_CLK_CTRL ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L ++ ++ ++// addressBlock: dcn_dcec_hpo_hdmi_frl_enc0_dispdec ++//HDMI_FRL_ENC_CONFIG ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L ++//HDMI_FRL_ENC_CONFIG2 ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 ++#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L ++//HDMI_FRL_ENC_METER_BUFFER_STATUS ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L ++//HDMI_FRL_ENC_MEM_CTRL ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L ++ ++ ++// addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_dispdec ++//HDMI_STREAM_ENC_CLOCK_CONTROL ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L ++//HDMI_STREAM_ENC_INPUT_MUX_CONTROL ++#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 ++#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L ++//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE__SHIFT 0x8 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE_MASK 0x00000100L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L ++//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L ++//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L ++ ++ + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec + //AFMT5_AFMT_VBI_PACKET_CONTROL + #define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT 0xd +@@ -60253,6 +60369,434 @@ + #define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + ++// addressBlock: dcn_dcec_hpo_hdmi_tb_enc0_dispdec ++//HDMI_TB_ENC_CONTROL ++#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 ++#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L ++//HDMI_TB_ENC_PIXEL_FORMAT ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L ++//HDMI_TB_ENC_PACKET_CONTROL ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L ++//HDMI_TB_ENC_ACR_PACKET_CONTROL ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L ++//HDMI_TB_ENC_VBI_PACKET_CONTROL1 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L ++//HDMI_TB_ENC_VBI_PACKET_CONTROL2 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L ++//HDMI_TB_ENC_GC_CONTROL ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L ++//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L ++//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L ++//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L ++//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L ++//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L ++//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L ++//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L ++//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L ++//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L ++//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L ++//HDMI_TB_ENC_GENERIC_PACKET14_LINE ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L ++//HDMI_TB_ENC_DB_CONTROL ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc ++#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L ++#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L ++//HDMI_TB_ENC_ACR_32_0 ++#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L ++//HDMI_TB_ENC_ACR_32_1 ++#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL ++//HDMI_TB_ENC_ACR_44_0 ++#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L ++//HDMI_TB_ENC_ACR_44_1 ++#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL ++//HDMI_TB_ENC_ACR_48_0 ++#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L ++//HDMI_TB_ENC_ACR_48_1 ++#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL ++//HDMI_TB_ENC_ACR_STATUS_0 ++#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L ++//HDMI_TB_ENC_ACR_STATUS_1 ++#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL ++//HDMI_TB_ENC_BUFFER_CONTROL ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L ++//HDMI_TB_ENC_MEM_CTRL ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L ++//HDMI_TB_ENC_METADATA_PACKET_CONTROL ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L ++//HDMI_TB_ENC_H_ACTIVE_BLANK ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L ++//HDMI_TB_ENC_HC_ACTIVE_BLANK ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L ++//HDMI_TB_ENC_CRC_CNTL ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L ++//HDMI_TB_ENC_CRC_RESULT_0 ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L ++//HDMI_TB_ENC_MODE ++#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 ++#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 ++#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L ++#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L ++//HDMI_TB_ENC_INPUT_FIFO_STATUS ++#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 ++#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L ++//HDMI_TB_ENC_CRC_RESULT_1 ++#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 ++#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL ++ ++ + // addressBlock: dce_dc_hpo_hpo_top_dispdec + //HPO_TOP_CLOCK_CONTROL + #define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT 0x0 +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h +index 16a69d17bb1e..4ada68f95b03 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h +@@ -8059,6 +8059,121 @@ + #define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + ++// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec ++// base address: 0x2656c ++#define regHDMI_LINK_ENC_CONTROL 0x095b ++#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 ++#define regHDMI_LINK_ENC_CLK_CTRL 0x095c ++#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 ++ ++ ++// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec ++// base address: 0x26594 ++#define regHDMI_FRL_ENC_CONFIG 0x0965 ++#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 ++#define regHDMI_FRL_ENC_CONFIG2 0x0966 ++#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 ++#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 ++#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 ++#define regHDMI_FRL_ENC_MEM_CTRL 0x0968 ++#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 ++ ++ ++// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec ++// base address: 0x2634c ++#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 ++#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 ++#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 ++ ++ ++// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec ++// base address: 0x2637c ++#define regHDMI_TB_ENC_CONTROL 0x08df ++#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 ++#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 ++#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 ++#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 ++#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 ++#define regHDMI_TB_ENC_GC_CONTROL 0x08e5 ++#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 ++#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea ++#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb ++#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec ++#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed ++#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee ++#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef ++#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 ++#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_DB_CONTROL 0x08f1 ++#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_32_0 0x08f2 ++#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_32_1 0x08f3 ++#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_44_0 0x08f4 ++#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_44_1 0x08f5 ++#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_48_0 0x08f6 ++#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_48_1 0x08f7 ++#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 ++#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 ++#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb ++#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_MEM_CTRL 0x08fe ++#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 ++#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff ++#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 ++#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 ++#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 ++#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 ++#define regHDMI_TB_ENC_CRC_CNTL 0x0903 ++#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 ++#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 ++#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ENCRYPTION_CONTROL 0x0907 ++#define regHDMI_TB_ENC_ENCRYPTION_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_MODE 0x0908 ++#define regHDMI_TB_ENC_MODE_BASE_IDX 3 ++#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 ++#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 ++#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a ++#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 ++ ++ ++ + // addressBlock: dce_dc_opp_dpg0_dispdec + // base address: 0x0 + #define regDPG0_DPG_CONTROL 0x1854 +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h +index 6473362e39a8..a2ab5fa3c2ec 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h +@@ -25949,6 +25949,507 @@ + #define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L ++ ++ ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 ++#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L ++ ++ ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L ++#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 ++#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE__SHIFT 0x8 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE_MASK 0x00000300L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L ++ ++ ++#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 ++#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc ++#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L ++#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L ++#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L ++#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL ++#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L ++#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL ++#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L ++#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL ++#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L ++#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L ++#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_ENABLE__SHIFT 0x0 ++#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_WHEN_AVMUTE__SHIFT 0x4 ++#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_ENABLE_MASK 0x00000001L ++#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_WHEN_AVMUTE_MASK 0x00000010L ++#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 ++#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 ++#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L ++#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L ++#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 ++#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L ++#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 ++#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL ++ ++ ++ + // addressBlock: dce_dc_opp_dpg0_dispdec + //DPG0_DPG_CONTROL + #define DPG0_DPG_CONTROL__DPG_EN__SHIFT 0x0 +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_offset.h +index a05bf8e4f58d..3a636a276e44 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_offset.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_offset.h +@@ -8520,6 +8520,120 @@ + #define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + ++// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec ++// base address: 0x2656c ++#define regHDMI_LINK_ENC_CONTROL 0x095b ++#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 ++#define regHDMI_LINK_ENC_CLK_CTRL 0x095c ++#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 ++ ++ ++// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec ++// base address: 0x26594 ++#define regHDMI_FRL_ENC_CONFIG 0x0965 ++#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 ++#define regHDMI_FRL_ENC_CONFIG2 0x0966 ++#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 ++#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 ++#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 ++#define regHDMI_FRL_ENC_MEM_CTRL 0x0968 ++#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 ++ ++ ++// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec ++// base address: 0x2634c ++#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 ++#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 ++#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 ++ ++ ++// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec ++// base address: 0x2637c ++#define regHDMI_TB_ENC_CONTROL 0x08df ++#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 ++#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 ++#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 ++#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 ++#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 ++#define regHDMI_TB_ENC_GC_CONTROL 0x08e5 ++#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 ++#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea ++#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb ++#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec ++#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed ++#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee ++#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef ++#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 ++#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_DB_CONTROL 0x08f1 ++#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_32_0 0x08f2 ++#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_32_1 0x08f3 ++#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_44_0 0x08f4 ++#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_44_1 0x08f5 ++#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_48_0 0x08f6 ++#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_48_1 0x08f7 ++#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 ++#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 ++#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb ++#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_MEM_CTRL 0x08fe ++#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 ++#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff ++#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 ++#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 ++#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 ++#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 ++#define regHDMI_TB_ENC_CRC_CNTL 0x0903 ++#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 ++#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 ++#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ENCRYPTION_CONTROL 0x0907 ++#define regHDMI_TB_ENC_ENCRYPTION_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_MODE 0x0908 ++#define regHDMI_TB_ENC_MODE_BASE_IDX 3 ++#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 ++#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 ++#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a ++#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 ++ ++ + // addressBlock: dce_dc_opp_dpg0_dispdec + // base address: 0x0 + #define regDPG0_DPG_CONTROL 0x1854 +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_sh_mask.h +index df84941bbe5b..8c2346d661ad 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_sh_mask.h +@@ -28690,6 +28690,507 @@ + #define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L ++ ++ ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 ++#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L ++ ++ ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L ++#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 ++#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE__SHIFT 0x8 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE_MASK 0x00000300L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L ++ ++ ++#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 ++#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc ++#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L ++#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L ++#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L ++#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL ++#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L ++#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL ++#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L ++#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL ++#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L ++#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L ++#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_ENABLE__SHIFT 0x0 ++#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_WHEN_AVMUTE__SHIFT 0x4 ++#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_ENABLE_MASK 0x00000001L ++#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_WHEN_AVMUTE_MASK 0x00000010L ++#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 ++#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 ++#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L ++#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L ++#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 ++#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L ++#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 ++#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL ++ ++ ++ + // addressBlock: dce_dc_opp_dpg0_dispdec + //DPG0_DPG_CONTROL + #define DPG0_DPG_CONTROL__DPG_EN__SHIFT 0x0 +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h +index 78cb61d5800a..8d04e861f16b 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h +@@ -7462,6 +7462,120 @@ + #define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + ++// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec ++// base address: 0x2656c ++#define regHDMI_LINK_ENC_CONTROL 0x095b ++#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 ++#define regHDMI_LINK_ENC_CLK_CTRL 0x095c ++#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 ++ ++ ++// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec ++// base address: 0x26594 ++#define regHDMI_FRL_ENC_CONFIG 0x0965 ++#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 ++#define regHDMI_FRL_ENC_CONFIG2 0x0966 ++#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 ++#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 ++#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 ++#define regHDMI_FRL_ENC_MEM_CTRL 0x0968 ++#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 ++ ++ ++// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec ++// base address: 0x2634c ++#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 ++#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 ++#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 ++ ++ ++// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec ++// base address: 0x2637c ++#define regHDMI_TB_ENC_CONTROL 0x08df ++#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 ++#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 ++#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 ++#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 ++#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 ++#define regHDMI_TB_ENC_GC_CONTROL 0x08e5 ++#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 ++#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea ++#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb ++#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec ++#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed ++#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee ++#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef ++#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 ++#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_DB_CONTROL 0x08f1 ++#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_32_0 0x08f2 ++#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_32_1 0x08f3 ++#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_44_0 0x08f4 ++#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_44_1 0x08f5 ++#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_48_0 0x08f6 ++#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_48_1 0x08f7 ++#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 ++#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 ++#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb ++#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_MEM_CTRL 0x08fe ++#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 ++#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff ++#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 ++#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 ++#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 ++#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 ++#define regHDMI_TB_ENC_CRC_CNTL 0x0903 ++#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 ++#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 ++#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ENCRYPTION_CONTROL 0x0907 ++#define regHDMI_TB_ENC_ENCRYPTION_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_MODE 0x0908 ++#define regHDMI_TB_ENC_MODE_BASE_IDX 3 ++#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 ++#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 ++#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a ++#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 ++ ++ + // addressBlock: dcn_dc_opp_dpg0_dispdec + // base address: 0x0 + #define regDPG0_DPG_CONTROL 0x1854 +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h +index c20bf730dc55..18d577ff90f6 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h +@@ -23157,6 +23157,507 @@ + #define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L ++ ++ ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 ++#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L ++ ++ ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L ++#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 ++#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE__SHIFT 0x8 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE_MASK 0x00000300L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L ++ ++ ++#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 ++#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc ++#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L ++#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L ++#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L ++#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL ++#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L ++#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL ++#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L ++#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL ++#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L ++#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L ++#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_ENABLE__SHIFT 0x0 ++#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_WHEN_AVMUTE__SHIFT 0x4 ++#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_ENABLE_MASK 0x00000001L ++#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_WHEN_AVMUTE_MASK 0x00000010L ++#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 ++#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 ++#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L ++#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L ++#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 ++#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L ++#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 ++#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL ++ ++ ++ + // addressBlock: dcn_dc_opp_dpg0_dispdec + //DPG0_DPG_CONTROL + #define DPG0_DPG_CONTROL__DPG_EN__SHIFT 0x0 +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h +index a04b8c32c564..2a316fd2544e 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h +@@ -7461,6 +7461,120 @@ + #define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + ++// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec ++// base address: 0x2656c ++#define regHDMI_LINK_ENC_CONTROL 0x095b ++#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 ++#define regHDMI_LINK_ENC_CLK_CTRL 0x095c ++#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 ++ ++ ++// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec ++// base address: 0x26594 ++#define regHDMI_FRL_ENC_CONFIG 0x0965 ++#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 ++#define regHDMI_FRL_ENC_CONFIG2 0x0966 ++#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 ++#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 ++#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 ++#define regHDMI_FRL_ENC_MEM_CTRL 0x0968 ++#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 ++ ++ ++// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec ++// base address: 0x2634c ++#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 ++#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 ++#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 ++#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 ++ ++ ++// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec ++// base address: 0x2637c ++#define regHDMI_TB_ENC_CONTROL 0x08df ++#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 ++#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 ++#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 ++#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 ++#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 ++#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 ++#define regHDMI_TB_ENC_GC_CONTROL 0x08e5 ++#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 ++#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 ++#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea ++#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb ++#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec ++#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed ++#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee ++#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef ++#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 ++#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 ++#define regHDMI_TB_ENC_DB_CONTROL 0x08f1 ++#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_32_0 0x08f2 ++#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_32_1 0x08f3 ++#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_44_0 0x08f4 ++#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_44_1 0x08f5 ++#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_48_0 0x08f6 ++#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_48_1 0x08f7 ++#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 ++#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 ++#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 ++#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb ++#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_MEM_CTRL 0x08fe ++#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 ++#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff ++#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 ++#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 ++#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 ++#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 ++#define regHDMI_TB_ENC_CRC_CNTL 0x0903 ++#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 ++#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 ++#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 ++#define regHDMI_TB_ENC_ENCRYPTION_CONTROL 0x0907 ++#define regHDMI_TB_ENC_ENCRYPTION_CONTROL_BASE_IDX 3 ++#define regHDMI_TB_ENC_MODE 0x0908 ++#define regHDMI_TB_ENC_MODE_BASE_IDX 3 ++#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 ++#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 ++#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a ++#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 ++ ++ + // addressBlock: dce_dc_opp_dpg0_dispdec + // base address: 0x0 + #define regDPG0_DPG_CONTROL 0x1854 +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h +index ce773fca621f..b083d9b614b5 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h +@@ -23133,6 +23133,507 @@ + #define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L ++#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L ++#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L ++ ++ ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L ++#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 ++#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L ++#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL ++#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L ++#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L ++ ++ ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L ++#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L ++#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 ++#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE__SHIFT 0x8 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE_MASK 0x00000300L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L ++ ++ ++#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 ++#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L ++#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L ++#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L ++#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L ++#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L ++#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L ++#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc ++#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L ++#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L ++#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L ++#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L ++#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL ++#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L ++#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL ++#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L ++#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL ++#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc ++#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L ++#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 ++#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L ++#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L ++#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L ++#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL ++#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L ++#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL ++#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L ++#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_ENABLE__SHIFT 0x0 ++#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_WHEN_AVMUTE__SHIFT 0x4 ++#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_ENABLE_MASK 0x00000001L ++#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_WHEN_AVMUTE_MASK 0x00000010L ++#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 ++#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 ++#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L ++#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L ++#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 ++#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L ++#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 ++#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL ++ ++ ++ + // addressBlock: dce_dc_opp_dpg0_dispdec + //DPG0_DPG_CONTROL + #define DPG0_DPG_CONTROL__DPG_EN__SHIFT 0x0 +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h +index ff77b71167eb..2e0a34493183 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h +@@ -52413,7 +52413,7 @@ + #define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +-#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE__SHIFT 0x8 + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +@@ -52421,7 +52421,7 @@ + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +-#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE_MASK 0x00000300L + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_1_sh_mask.h +index d0e95d324053..8859272970b7 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_1_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_1_sh_mask.h +@@ -52392,7 +52392,7 @@ + #define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +-#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE__SHIFT 0x8 + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +@@ -52400,7 +52400,7 @@ + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +-#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE_MASK 0x00000300L + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h +index 3ffb6ec8b40a..2b461f3f2e5d 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h +@@ -48669,7 +48669,7 @@ + //HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +-#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE__SHIFT 0x8 + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +@@ -48677,7 +48677,7 @@ + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +-#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L ++#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE_MASK 0x00000300L + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L + #define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +diff --git a/drivers/gpu/drm/amd/include/atombios.h b/drivers/gpu/drm/amd/include/atombios.h +index b344acefc606..3969abd2fdb7 100644 +--- a/drivers/gpu/drm/amd/include/atombios.h ++++ b/drivers/gpu/drm/amd/include/atombios.h +@@ -1588,6 +1588,7 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6 + #define ATOM_TRANSMITTER_DIGMODE_V6_DP 0 + #define ATOM_TRANSMITTER_DIGMODE_V6_DVI 2 + #define ATOM_TRANSMITTER_DIGMODE_V6_HDMI 3 ++#define ATOM_TRANSMITTER_DIGMODE_V6_HDMI_FRL 4 + #define ATOM_TRANSMITTER_DIGMODE_V6_DP_MST 5 + + //ucHPDSel +diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h +index 3d083010e734..6949baf76737 100644 +--- a/drivers/gpu/drm/amd/include/atomfirmware.h ++++ b/drivers/gpu/drm/amd/include/atomfirmware.h +@@ -97,6 +97,7 @@ enum atom_encode_mode_def + ATOM_ENCODER_MODE_LVDS =1, + ATOM_ENCODER_MODE_DVI =2, + ATOM_ENCODER_MODE_HDMI =3, ++ ATOM_ENCODER_MODE_HDMI_FRL =4, + ATOM_ENCODER_MODE_DP_AUDIO =5, + ATOM_ENCODER_MODE_DP_MST =5, + ATOM_ENCODER_MODE_CRT =15, +diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c +index a697cc227e28..d0950a204b21 100644 +--- a/drivers/gpu/drm/display/drm_dp_helper.c ++++ b/drivers/gpu/drm/display/drm_dp_helper.c +@@ -3904,7 +3904,7 @@ void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, + int i, num_error; + struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; + +- for (i = 0; i < hdmi->max_lanes; i++) { ++ for (i = 0; i < hdmi->frl_cap.max_lanes; i++) { + if (drm_dp_dpcd_read_byte(aux, DP_PCON_HDMI_ERROR_STATUS_LN0 + i, &buf) < 0) + return; + +diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c +index dc013a22bf26..f7874005f33a 100644 +--- a/drivers/gpu/drm/drm_atomic_uapi.c ++++ b/drivers/gpu/drm/drm_atomic_uapi.c +@@ -412,6 +412,8 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, + return ret; + } else if (property == config->prop_vrr_enabled) { + state->vrr_enabled = val; ++ } else if (property == config->prop_passive_vrr_disabled) { ++ state->passive_vrr_disabled = val; + } else if (property == config->degamma_lut_property) { + const size_t elem_size = sizeof(struct drm_color_lut); + u64 lut_size; +@@ -495,6 +497,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc, + *val = (state->mode_blob) ? state->mode_blob->base.id : 0; + else if (property == config->prop_vrr_enabled) + *val = state->vrr_enabled; ++ else if (property == config->prop_passive_vrr_disabled) ++ *val = state->passive_vrr_disabled; + else if (property == config->degamma_lut_property) + *val = (state->degamma_lut) ? state->degamma_lut->base.id : 0; + else if (property == config->ctm_property) +@@ -901,6 +905,8 @@ static int drm_atomic_connector_set_property(struct drm_connector *connector, + state->content_type = val; + } else if (property == connector->scaling_mode_property) { + state->scaling_mode = val; ++ } else if (property == connector->allm_mode_property) { ++ state->allm_mode = val; + } else if (property == config->content_protection_property) { + if (val == DRM_MODE_CONTENT_PROTECTION_ENABLED) { + drm_dbg_kms(dev, "only drivers can set CP Enabled\n"); +@@ -998,6 +1004,8 @@ drm_atomic_connector_get_property(struct drm_connector *connector, + *val = state->colorspace; + } else if (property == connector->scaling_mode_property) { + *val = state->scaling_mode; ++ } else if (property == connector->allm_mode_property) { ++ *val = state->allm_mode; + } else if (property == config->hdr_output_metadata_property) { + *val = state->hdr_output_metadata ? + state->hdr_output_metadata->base.id : 0; +diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c +index 4f5b27fab475..38d649a11a93 100644 +--- a/drivers/gpu/drm/drm_connector.c ++++ b/drivers/gpu/drm/drm_connector.c +@@ -1232,6 +1232,12 @@ static const struct drm_prop_enum_list drm_content_type_enum_list[] = { + { DRM_MODE_CONTENT_TYPE_GAME, "Game" }, + }; + ++static const struct drm_prop_enum_list drm_allm_mode_enum_list[] = { ++ { DRM_ALLM_MODE_DISABLED, "Disabled" }, ++ { DRM_ALLM_MODE_ENABLED_DYNAMIC, "Dynamic" }, ++ { DRM_ALLM_MODE_ENABLED_FORCED, "Always On" }, ++}; ++ + static const struct drm_prop_enum_list drm_panel_orientation_enum_list[] = { + { DRM_MODE_PANEL_ORIENTATION_NORMAL, "Normal" }, + { DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP, "Upside Down" }, +@@ -2352,6 +2358,16 @@ EXPORT_SYMBOL(drm_mode_create_scaling_mode_property); + * + * Absence of the property should indicate absence of support. + * ++ * "passive_vrr_capable": ++ * Optional &drm_connector boolean property that drivers should attach ++ * with drm_connector_attach_passive_vrr_capable_property() on ++ * connectors that could support keeping variable refresh rate signalling ++ * in fixed-refresh rate scenarios like desktop work. Drivers should update ++ * the property value by calling ++ * drm_connector_set_passive_vrr_capable_property(). ++ * ++ * Absence of the property should indicate absence of support. ++ * + * "VRR_ENABLED": + * Default &drm_crtc boolean property that notifies the driver that the + * content on the CRTC is suitable for variable refresh rate presentation. +@@ -2370,6 +2386,17 @@ EXPORT_SYMBOL(drm_mode_create_scaling_mode_property); + * + * The driver may place further restrictions within these minimum + * and maximum bounds. ++ * ++ * "PASSIVE_VRR_DISABLED": ++ * Default &drm_crtc boolean property that notifies the driver that the ++ * VRR singalling should be disabled in fixed refresh rate scenarios. ++ * Functionally, psssive vrr works the same as VRR_ENABLED == false ++ * but works around displays blanking (mainly HDMI) that do not support ++ * seamless VRR transitions. Also helps with brightness flickering during ++ * VRR transitions. ++ * ++ * Passive VRR mode is not that useful for DP/eDP sinks where seamless VRR ++ * transitions are enforced by the standard. + */ + + /** +@@ -2403,6 +2430,125 @@ int drm_connector_attach_vrr_capable_property( + } + EXPORT_SYMBOL(drm_connector_attach_vrr_capable_property); + ++/** ++ * drm_connector_attach_passive_vrr_capable_property - creates the ++ * passive_vrr_capable property ++ * @connector: connector to create the passive_vrr_capable property on. ++ * ++ * This is used by atomic drivers to add support for querying ++ * variable refresh rate on desktop capability for a connector. ++ * ++ * Returns: ++ * Zero on success, negative errno on failure. ++ */ ++int drm_connector_attach_passive_vrr_capable_property( ++ struct drm_connector *connector) ++{ ++ struct drm_device *dev = connector->dev; ++ struct drm_property *prop; ++ ++ if (!connector->passive_vrr_capable_property) { ++ prop = drm_property_create_bool(dev, DRM_MODE_PROP_IMMUTABLE, ++ "passive_vrr_capable"); ++ if (!prop) ++ return -ENOMEM; ++ ++ connector->passive_vrr_capable_property = prop; ++ drm_object_attach_property(&connector->base, prop, 0); ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(drm_connector_attach_passive_vrr_capable_property); ++ ++/** ++ * DOC: Auto Low Latency Mode properties ++ * ++ * Auto Low Latency capable HDMI displays (be it PC monitors or TVs) ++ * can automatically enter a "low latency" mode, usually named "Game Mode" by ++ * receiving specific data in HDMI Forum vendor-specific info frame. ++ * ++ * This usually is the best mode for PC usage but disables as much processing as ++ * possible which might not be desireable on lower end devices casing them to ++ * produce an image that's unsatisfactory to some users. ++ * ++ * "allm_capable": ++ * Optional &drm_connector boolean property that drivers should attach ++ * with drm_connector_attach_allm_capable_property() on connectors that ++ * could support Auto Low Latency Mode. Drivers should update the ++ * property value by calling drm_connector_set_allm_capable_property(). ++ * ++ * Absence of the property should indicate absence of support. ++ * ++ * "ALLM_MODE": ++ * Optional &drm_connector enum property enables compositors to control and ++ * expose ALLM triggering behavior modes to the end user where: ++ * ++ * - ALLM_MODE_DISABLED: completely disabled ALLM signalling. ++ * - ALLM_MODE_ENABLED_DYNAMIC: triggers ALLM based on current needs. ++ * preferrably display content type hint being set to Game by compositor ++ * or VRR being enabled and active. ++ * - ALLM_MODE_ENABLED_FORCED: always-on ALLM triggering. ++ * ++ * ALLM_MODE_ENABLED_DYNAMIC should behave like gaming devices such as ++ * consoles where ALLM is only triggered when needed. It's main purpose is ++ * gaming (part of so-called HDMI gaming features). ++ * ++ * If compositors wish to control ALLM completely on their own, they can ++ * switch between disabled and enabled_forced modes. ++ */ ++ ++/** ++ * drm_connector_attach_allm_capable_property - creates the ++ * allm_capable property ++ * @connector: connector to create the allm_capable property on. ++ * ++ * This is used by atomic drivers to add support for querying ++ * Auto Low Latency Mode capability for a connector. ++ * ++ * Returns: ++ * Zero on success, negative errno on failure. ++ */ ++int drm_connector_attach_allm_capable_property(struct drm_connector *connector) ++{ ++ struct drm_device *dev = connector->dev; ++ struct drm_property *prop; ++ ++ if (!connector->allm_capable_property) { ++ prop = drm_property_create_bool(dev, DRM_MODE_PROP_IMMUTABLE, ++ "allm_capable"); ++ if (!prop) ++ return -ENOMEM; ++ ++ connector->allm_capable_property = prop; ++ drm_object_attach_property(&connector->base, prop, 0); ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(drm_connector_attach_allm_capable_property); ++ ++int drm_connector_attach_allm_mode_property(struct drm_connector *connector) ++{ ++ struct drm_property *prop; ++ ++ if (connector->allm_mode_property) ++ return 0; ++ ++ prop = drm_property_create_enum(connector->dev, 0, "allm_mode", ++ drm_allm_mode_enum_list, ++ ARRAY_SIZE(drm_allm_mode_enum_list)); ++ if (!prop) ++ return -ENOMEM; ++ ++ connector->allm_mode_property = prop; ++ drm_object_attach_property(&connector->base, prop, ++ DRM_ALLM_MODE_DISABLED); ++ ++ return 0; ++} ++EXPORT_SYMBOL(drm_connector_attach_allm_mode_property); ++ + /** + * drm_connector_attach_scaling_mode_property - attach atomic scaling mode property + * @connector: connector to attach scaling mode property on. +@@ -2974,6 +3120,48 @@ void drm_connector_set_vrr_capable_property( + } + EXPORT_SYMBOL(drm_connector_set_vrr_capable_property); + ++/** ++ * drm_connector_set_passive_vrr_disabled_capable_property - sets the variable refresh ++ * rate on desktop capable property for a connector ++ * @connector: drm connector ++ * @capable: True if the connector is variable refresh rate on desktop capable ++ * ++ * Should be used by atomic drivers to update the indicated support for ++ * variable refresh rate on desktop over a connector. ++ */ ++void drm_connector_set_passive_vrr_capable_property( ++ struct drm_connector *connector, bool capable) ++{ ++ if (!connector->passive_vrr_capable_property) ++ return; ++ ++ drm_object_property_set_value(&connector->base, ++ connector->passive_vrr_capable_property, ++ capable); ++} ++EXPORT_SYMBOL(drm_connector_set_passive_vrr_capable_property); ++ ++/** ++ * drm_connector_set_allm_capable_property - sets Auto Low Latency Mode ++ * capable property for a connector ++ * @connector: drm connector ++ * @capable: True if the connector is ALLM capable ++ * ++ * Should be used by atomic drivers to update the indicated support for ++ * Auto Low Latency Mode over a connector. ++ */ ++void drm_connector_set_allm_capable_property( ++ struct drm_connector *connector, bool capable) ++{ ++ if (!connector->allm_capable_property) ++ return; ++ ++ drm_object_property_set_value(&connector->base, ++ connector->allm_capable_property, ++ capable); ++} ++EXPORT_SYMBOL(drm_connector_set_allm_capable_property); ++ + /** + * drm_connector_set_panel_orientation - sets the connector's panel_orientation + * @connector: connector for which to set the panel-orientation property. +diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c +index a7797d260f1e..4f2c871552e5 100644 +--- a/drivers/gpu/drm/drm_crtc.c ++++ b/drivers/gpu/drm/drm_crtc.c +@@ -322,6 +322,8 @@ static int __drm_crtc_init_with_planes(struct drm_device *dev, struct drm_crtc * + config->prop_out_fence_ptr, 0); + drm_object_attach_property(&crtc->base, + config->prop_vrr_enabled, 0); ++ drm_object_attach_property(&crtc->base, ++ config->prop_passive_vrr_disabled, 0); + } + + return 0; +diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c +index 26bb7710a462..50ec021dbce2 100644 +--- a/drivers/gpu/drm/drm_edid.c ++++ b/drivers/gpu/drm/drm_edid.c +@@ -6108,38 +6108,44 @@ static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) + } + + static +-void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) ++void drm_parse_max_frl_rate(int max_frl_rate, struct drm_hdmi_frl_cap *frl) + { ++ u8 max_lanes, max_rate_per_lane; ++ + switch (max_frl_rate) { + case 1: +- *max_lanes = 3; +- *max_rate_per_lane = 3; ++ max_lanes = 3; ++ max_rate_per_lane = 3; + break; + case 2: +- *max_lanes = 3; +- *max_rate_per_lane = 6; ++ max_lanes = 3; ++ max_rate_per_lane = 6; + break; + case 3: +- *max_lanes = 4; +- *max_rate_per_lane = 6; ++ max_lanes = 4; ++ max_rate_per_lane = 6; + break; + case 4: +- *max_lanes = 4; +- *max_rate_per_lane = 8; ++ max_lanes = 4; ++ max_rate_per_lane = 8; + break; + case 5: +- *max_lanes = 4; +- *max_rate_per_lane = 10; ++ max_lanes = 4; ++ max_rate_per_lane = 10; + break; + case 6: +- *max_lanes = 4; +- *max_rate_per_lane = 12; ++ max_lanes = 4; ++ max_rate_per_lane = 12; + break; + case 0: + default: +- *max_lanes = 0; +- *max_rate_per_lane = 0; ++ max_lanes = 0; ++ max_rate_per_lane = 0; + } ++ ++ frl->max_lanes = max_lanes; ++ frl->max_rate = max_frl_rate; ++ frl->max_rate_per_lane = max_rate_per_lane; + } + + static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, +@@ -6152,6 +6158,33 @@ static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, + hdmi->y420_dc_modes = dc_mask; + } + ++static void drm_parse_hdmi_gaming_info(struct drm_hdmi_info *hdmi, const u8 *db) ++{ ++ struct drm_hdmi_vrr_cap *vrr = &hdmi->vrr_cap; ++ ++ if (cea_db_payload_len(db) < 8) ++ return; ++ ++ hdmi->fapa_start_location = db[8] & DRM_EDID_FAPA_START_LOCATION; ++ hdmi->allm = db[8] & DRM_EDID_ALLM; ++ vrr->fva = db[8] & DRM_EDID_FVA; ++ vrr->cnmvrr = db[8] & DRM_EDID_CNMVRR; ++ vrr->cinema_vrr = db[8] & DRM_EDID_CINEMA_VRR; ++ vrr->mdelta = db[8] & DRM_EDID_MDELTA; ++ ++ if (cea_db_payload_len(db) < 9) ++ return; ++ ++ vrr->vrr_min = db[9] & DRM_EDID_VRR_MIN_MASK; ++ vrr->supported = (vrr->vrr_min > 0 && vrr->vrr_min <= 48); ++ ++ if (cea_db_payload_len(db) < 10) ++ return; ++ ++ vrr->vrr_max = (db[9] & DRM_EDID_VRR_MAX_UPPER_MASK) << 2 | db[10]; ++ vrr->supported &= (vrr->vrr_max == 0 || vrr->vrr_max >= 100); ++} ++ + static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc, + const u8 *hf_scds) + { +@@ -6178,8 +6211,7 @@ static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc, + u8 dsc_max_frl_rate; + + dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; +- drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, +- &hdmi_dsc->max_frl_rate_per_lane); ++ drm_parse_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->frl_cap); + + dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES; + +@@ -6272,12 +6304,11 @@ static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, + + if (hf_scds[7]) { + max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; +- drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, +- &hdmi->max_frl_rate_per_lane); ++ drm_parse_max_frl_rate(max_frl_rate, &hdmi->frl_cap); + } + + drm_parse_ycbcr420_deep_color_info(connector, hf_scds); +- ++ drm_parse_hdmi_gaming_info(&connector->display_info.hdmi, hf_scds); + if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) { + drm_parse_dsc_info(hdmi_dsc, hf_scds); + dsc_support = true; +@@ -6287,6 +6318,18 @@ static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, + "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n", + connector->base.id, connector->name, + max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support)); ++ drm_dbg_kms(connector->dev, ++ "[CONNECTOR:%d:%s] FAPA in blanking: %s, ALLM support: %s, Fast Vactive support: %s\n", ++ connector->base.id, connector->name, str_yes_no(hdmi->fapa_start_location), ++ str_yes_no(hdmi->allm), str_yes_no(hdmi->vrr_cap.fva)); ++ drm_dbg_kms(connector->dev, ++ "[CONNECTOR:%d:%s] Negative M VRR support: %s, CinemaVRR support: %s, Mdelta: %d\n", ++ connector->base.id, connector->name, str_yes_no(hdmi->vrr_cap.cnmvrr), ++ str_yes_no(hdmi->vrr_cap.cinema_vrr), hdmi->vrr_cap.mdelta); ++ drm_dbg_kms(connector->dev, ++ "[CONNECTOR:%d:%s] VRRmin: %u, VRRmax: %u, VRR supported: %s\n", ++ connector->base.id, connector->name, hdmi->vrr_cap.vrr_min, ++ hdmi->vrr_cap.vrr_max, str_yes_no(hdmi->vrr_cap.supported)); + } + + static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, +diff --git a/drivers/gpu/drm/drm_mode_config.c b/drivers/gpu/drm/drm_mode_config.c +index d12db9b0bab8..231f54ba66f8 100644 +--- a/drivers/gpu/drm/drm_mode_config.c ++++ b/drivers/gpu/drm/drm_mode_config.c +@@ -345,6 +345,12 @@ static int drm_mode_create_standard_properties(struct drm_device *dev) + return -ENOMEM; + dev->mode_config.prop_vrr_enabled = prop; + ++ prop = drm_property_create_bool(dev, 0, ++ "PASSIVE_VRR_DISABLED"); ++ if (!prop) ++ return -ENOMEM; ++ dev->mode_config.prop_passive_vrr_disabled = prop; ++ + prop = drm_property_create(dev, + DRM_MODE_PROP_BLOB, + "DEGAMMA_LUT", 0); +diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c +index 7e022c47e8ac..38191d2edc3c 100644 +--- a/drivers/gpu/drm/i915/display/intel_dp.c ++++ b/drivers/gpu/drm/i915/display/intel_dp.c +@@ -3945,13 +3945,13 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) + int max_lanes, rate_per_lane; + int max_dsc_lanes, dsc_rate_per_lane; + +- max_lanes = info->hdmi.max_lanes; +- rate_per_lane = info->hdmi.max_frl_rate_per_lane; ++ max_lanes = info->hdmi.frl_cap.max_lanes; ++ rate_per_lane = info->hdmi.frl_cap.max_rate_per_lane; + max_frl_rate = max_lanes * rate_per_lane; + + if (info->hdmi.dsc_cap.v_1p2) { +- max_dsc_lanes = info->hdmi.dsc_cap.max_lanes; +- dsc_rate_per_lane = info->hdmi.dsc_cap.max_frl_rate_per_lane; ++ max_dsc_lanes = info->hdmi.dsc_cap.frl_cap.max_lanes; ++ dsc_rate_per_lane = info->hdmi.dsc_cap.frl_cap.max_rate_per_lane; + if (max_dsc_lanes && dsc_rate_per_lane) + max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane); + } +diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h +index 7eaec37ae1c7..cc17c17e3103 100644 +--- a/include/drm/drm_connector.h ++++ b/include/drm/drm_connector.h +@@ -58,6 +58,12 @@ enum drm_connector_force { + DRM_FORCE_ON_DIGITAL, /* for DVI-I use digital connector */ + }; + ++enum drm_allm_mode { ++ DRM_ALLM_MODE_DISABLED, ++ DRM_ALLM_MODE_ENABLED_DYNAMIC, ++ DRM_ALLM_MODE_ENABLED_FORCED, ++}; ++ + /** + * enum drm_connector_status - status for a &drm_connector + * +@@ -254,6 +260,62 @@ struct drm_scdc { + struct drm_scrambling scrambling; + }; + ++/** ++ * struct drm_hdmi_frl_cap - FRL capabilities of HDMI sink ++ * ++ * Describes the FRL support provided by HDMI 2.1 sink. ++ * The information is fetched fom additional HFVSDB blocks defined ++ * for HDMI 2.1. ++ */ ++struct drm_hdmi_frl_cap { ++ /** @max_rate: raw max rate value without parsing */ ++ u8 max_rate; ++ ++ /** @max_frl_rate_per_lane: support fixed rate link */ ++ u8 max_rate_per_lane; ++ ++ /** @max_lanes: supported by sink */ ++ u8 max_lanes; ++}; ++ ++/* ++ * struct drm_hdmi_vrr_cap - Information about VRR capabilities of a HDMI sink ++ * ++ * Describes the VRR support provided by HDMI 2.1 sink. The information is ++ * fetched fom additional HFVSDB blocks defined for HDMI 2.1. ++ */ ++struct drm_hdmi_vrr_cap { ++ /** @fva: flag for Fast VActive (Quick Frame Transport) support */ ++ bool fva; ++ ++ /** @mcnmvrr: flag for Negative M VRR support */ ++ bool cnmvrr; ++ ++ /** @mcinema_vrr: flag for Cinema VRR support */ ++ bool cinema_vrr; ++ ++ /** @mdelta: flag for limited frame-to-frame compensation support */ ++ bool mdelta; ++ ++ /** ++ * @vrr_min : minimum supported variable refresh rate in Hz. ++ * Valid values only inide 1 - 48 range ++ */ ++ u16 vrr_min; ++ ++ /** ++ * @vrr_max : maximum supported variable refresh rate in Hz (optional). ++ * Valid values are either 0 (max based on video mode) or >= 100 ++ */ ++ u16 vrr_max; ++ ++ /** ++ * @supported: flag for vrr support based on checking for VRRmin and ++ * VRRmax values having correct values. ++ */ ++ bool supported; ++}; ++ + /** + * struct drm_hdmi_dsc_cap - DSC capabilities of HDMI sink + * +@@ -285,14 +347,11 @@ struct drm_hdmi_dsc_cap { + /** @clk_per_slice : max pixel clock in MHz supported per slice */ + int clk_per_slice; + +- /** @max_lanes : dsc max lanes supported for Fixed rate Link training */ +- u8 max_lanes; +- +- /** @max_frl_rate_per_lane : maximum frl rate with DSC per lane */ +- u8 max_frl_rate_per_lane; +- + /** @total_chunk_kbytes: max size of chunks in KBs supported per line*/ + u8 total_chunk_kbytes; ++ ++ /** @frl_cap: FRL under DSC capabilities of the sink */ ++ struct drm_hdmi_frl_cap frl_cap; + }; + + /** +@@ -324,11 +383,17 @@ struct drm_hdmi_info { + /** @y420_dc_modes: bitmap of deep color support index */ + u8 y420_dc_modes; + +- /** @max_frl_rate_per_lane: support fixed rate link */ +- u8 max_frl_rate_per_lane; ++ /** @frl_cap: FRL capabilities of the sink */ ++ struct drm_hdmi_frl_cap frl_cap; + +- /** @max_lanes: supported by sink */ +- u8 max_lanes; ++ /** @fapa_start_location: flag for the FAPA in blanking support */ ++ bool fapa_start_location; ++ ++ /** @allm: flag for Auto Low Latency Mode support by sink */ ++ bool allm; ++ ++ /** @vrr_cap: VRR capabilities of the sink */ ++ struct drm_hdmi_vrr_cap vrr_cap; + + /** @dsc_cap: DSC capabilities of the sink */ + struct drm_hdmi_dsc_cap dsc_cap; +@@ -1100,6 +1165,13 @@ struct drm_connector_state { + */ + unsigned int content_protection; + ++ /** ++ * @allm_mode: Connector property to control the ++ * HDMI Auto Low Latency Mode trigger setting. ++ * The %DRM_ALLM_MODE_\* values must match the values. ++ */ ++ enum drm_allm_mode allm_mode; ++ + /** + * @colorspace: State variable for Connector property to request + * colorspace change on Sink. This is most commonly used to switch +@@ -2099,6 +2171,37 @@ struct drm_connector { + */ + struct drm_property *vrr_capable_property; + ++ /** ++ * @passive_vrr_capable_property: Optional property to help userspace ++ * query hardware support for passive variable refresh rate on a ++ * connector. Drivers can add the property to a connector by ++ * calling drm_connector_attach_passive_vrr_capable_property(). ++ * ++ * This should be updated only by calling ++ * drm_connector_set_passive_vrr_capable_property(). ++ */ ++ struct drm_property *passive_vrr_capable_property; ++ ++ /** ++ * @allm_capable_property: Optional property to help userspace ++ * query hardware support for HDMI Auto Low Latency Mode on a connector. ++ * Drivers can add the property to a connector by calling ++ * drm_connector_attach_allm_capable_property(). ++ * ++ * This should be updated only by calling ++ * drm_connector_set_allm_capable_property(). ++ */ ++ struct drm_property *allm_capable_property; ++ ++ /** ++ * @allm_mode_property: ++ * ++ * Indicates HDMI Auto Low Latency Mode triggering mode for connector. ++ * Support for the requested state will depend on driver and hardware ++ * capabiltiy - lacking support is not treated as failure. ++ */ ++ struct drm_property *allm_mode_property; ++ + /** + * @colorspace_property: Connector property to set the suitable + * colorspace supported by the sink. +@@ -2493,6 +2596,10 @@ int drm_connector_attach_scaling_mode_property(struct drm_connector *connector, + u32 scaling_mode_mask); + int drm_connector_attach_vrr_capable_property( + struct drm_connector *connector); ++int drm_connector_attach_passive_vrr_capable_property( ++ struct drm_connector *connector); ++int drm_connector_attach_allm_capable_property(struct drm_connector *connector); ++int drm_connector_attach_allm_mode_property(struct drm_connector *connector); + int drm_connector_attach_broadcast_rgb_property(struct drm_connector *connector); + int drm_connector_attach_colorspace_property(struct drm_connector *connector); + int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *connector); +@@ -2515,6 +2622,10 @@ void drm_connector_set_link_status_property(struct drm_connector *connector, + uint64_t link_status); + void drm_connector_set_vrr_capable_property( + struct drm_connector *connector, bool capable); ++void drm_connector_set_passive_vrr_capable_property( ++ struct drm_connector *connector, bool capable); ++void drm_connector_set_allm_capable_property( ++ struct drm_connector *connector, bool capable); + int drm_connector_set_panel_orientation( + struct drm_connector *connector, + enum drm_panel_orientation panel_orientation); +diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h +index 66278ffeebd6..59dbb7ce1358 100644 +--- a/include/drm/drm_crtc.h ++++ b/include/drm/drm_crtc.h +@@ -299,6 +299,15 @@ struct drm_crtc_state { + */ + bool vrr_enabled; + ++ /** ++ * @passive_vrr_disabled: ++ * ++ * Indicates if variable refresh rate on desktop should be enabled for ++ * the CRTC. Support for the requested state will depend on driver and ++ * hardware capabiltiy - lacking support is not treated as failure. ++ */ ++ bool passive_vrr_disabled; ++ + /** + * @self_refresh_active: + * +diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h +index 895fb820dba0..23ce744b233b 100644 +--- a/include/drm/drm_mode_config.h ++++ b/include/drm/drm_mode_config.h +@@ -697,6 +697,12 @@ struct drm_mode_config { + * whether variable refresh rate should be enabled on the CRTC. + */ + struct drm_property *prop_vrr_enabled; ++ /** ++ * @prop_passive_vrr_disabled: Default atomic CRTC property to indicate ++ * whether passive variable refresh rate should be disabled ++ * on the CRTC. ++ */ ++ struct drm_property *prop_passive_vrr_disabled; + + /** + * @dvi_i_subconnector_property: Optional DVI-I property to